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llvm-project/llvm/lib/Target/Hexagon
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Simon Pilgrim b1f38a27f0 [Target][CodeGen] Remove default CostKind arguments on inner/impl TTI overrides 
Based off a discussion on D110100, we should be avoiding default CostKinds whenever possible.

This initial patch removes them from the 'inner' target implementation callbacks - these should only be used by the main TTI calls, so this should guarantee that we don't cause changes in CostKind by missing it in an inner call. This exposed a few missing arguments in getGEPCost and reduction cost calls that I've cleaned up.

Differential Revision: https://reviews.llvm.org/D110242
 		2021-09-22 15:28:08 +01:00
..
AsmParser [MC] Add MCSubtargetInfo to MCAlignFragment 2021-09-07 15:46:19 +01:00
Disassembler [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
MCTargetDesc [MC] Use local MCSubtargetInfo in writeNops 2021-09-07 15:46:19 +01:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
BitTracker.cpp [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
BitTracker.h [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
CMakeLists.txt [Hexagon] Remove redundant HVX intrinsic selection patterns, NFC 2021-04-23 09:28:08 -05:00
Hexagon.h
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Hexagon.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonArch.h
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HexagonAsmPrinter.cpp [MC] Add MCSubtargetInfo to MCAlignFragment 2021-09-07 15:46:19 +01:00
HexagonAsmPrinter.h
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HexagonBitSimplify.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonBitTracker.cpp [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
HexagonBitTracker.h [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 2020-12-02 15:46:38 -08:00
HexagonBlockRanges.cpp [llvm] Use llvm::sort (NFC) 2021-01-17 10:39:45 -08:00
HexagonBlockRanges.h [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonBranchRelaxation.cpp [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
HexagonCFGOptimizer.cpp
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HexagonCallingConv.td
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HexagonCommonGEP.cpp [Hexagon] Opaquify pointer usage in GEP commoning 2021-06-24 16:06:36 -05:00
HexagonConstExtenders.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonConstPropagation.cpp [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
HexagonCopyToCombine.cpp
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HexagonDepArch.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepArch.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepDecoders.inc [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepIICHVX.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepIICScalar.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepITypes.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepITypes.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepInstrFormats.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepInstrInfo.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMapAsm2Intrin.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMappings.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepMask.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepOperands.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonDepTimingClasses.h [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonEarlyIfConv.cpp [CodeGen, Target] Use pred_empty and succ_empty (NFC) 2021-09-10 11:11:31 -07:00
HexagonExpandCondsets.cpp [llvm] Use *::empty (NFC) 2021-01-16 09:40:55 -08:00
HexagonFixupHwLoops.cpp
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HexagonFrameLowering.cpp Rename MachineMemOperand::getOrdering -> getSuccessOrdering. 2021-06-21 16:49:27 -07:00
HexagonFrameLowering.h [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
HexagonGenExtract.cpp
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HexagonGenInsert.cpp [Target] Use llvm::erase_if (NFC) 2020-12-20 17:43:22 -08:00
HexagonGenMux.cpp [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
HexagonGenPredicate.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonHardwareLoops.cpp [InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI) 2021-08-30 19:46:04 +02:00
HexagonHazardRecognizer.cpp
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HexagonHazardRecognizer.h
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HexagonIICHVX.td
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HexagonIICScalar.td
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HexagonISelDAGToDAG.cpp [SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode. 2021-09-09 13:28:30 -07:00
HexagonISelDAGToDAG.h
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HexagonISelDAGToDAGHVX.cpp [Hexagon] Restore handling of expanding shuffles 2021-05-26 18:04:15 -05:00
HexagonISelLowering.cpp [SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode. 2021-09-09 13:28:30 -07:00
HexagonISelLowering.h [Hexagon] Generate trap/undef if misaligned access is detected 2021-07-06 14:52:23 -05:00
HexagonISelLoweringHVX.cpp [Hexagon] Handle bitcast of i64/i128 -> v64i1/v128i1 2021-09-13 18:52:30 -05:00
HexagonInstrFormats.td [Hexagon] NFC: Remove unused tblgen template args 2021-09-13 10:09:08 +00:00
HexagonInstrFormatsV60.td
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HexagonInstrFormatsV65.td
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HexagonInstrInfo.cpp [InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI) 2021-08-30 19:46:04 +02:00
HexagonInstrInfo.h [InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI) 2021-08-30 19:46:04 +02:00
HexagonIntrinsics.td [Hexagon] Remove redundant HVX intrinsic selection patterns, NFC 2021-04-23 09:28:08 -05:00
HexagonIntrinsicsV5.td
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HexagonIntrinsicsV60.td
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HexagonLoopIdiomRecognition.cpp Require chained analyses in BasicAA and AAResults to be transitive 2021-01-11 11:50:07 +01:00
HexagonLoopIdiomRecognition.h [Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline 2020-11-20 09:34:37 -08:00
HexagonMCInstLower.cpp
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HexagonMachineFunctionInfo.cpp
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HexagonMachineFunctionInfo.h
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HexagonMachineScheduler.cpp
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HexagonMachineScheduler.h
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HexagonMapAsm2IntrinV62.gen.td
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HexagonNewValueJump.cpp
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HexagonOperands.td
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HexagonOptAddrMode.cpp
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HexagonOptimizeSZextends.cpp [NFC] Clean up users of AttributeList::hasAttribute() 2021-08-13 11:59:18 -07:00
HexagonPatterns.td [Hexagon] Add patterns to load i1 2021-06-28 12:17:30 -05:00
HexagonPatternsHVX.td [Hexagon] Use 'vnot' instead of 'not' in patterns with vectors 2021-04-22 15:36:20 -05:00
HexagonPatternsV65.td
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HexagonPeephole.cpp [NFC] Use [MC]Register for Hexagon target 2020-11-18 08:17:07 -08:00
HexagonPseudo.td [Hexagon] NFC: Remove unused tblgen template args 2021-09-13 10:09:08 +00:00
HexagonRDFOpt.cpp
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HexagonRegisterInfo.cpp [Hexagon] Limit virtual register reuse range in FI elimination 2021-03-25 13:59:36 -05:00
HexagonRegisterInfo.h
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HexagonRegisterInfo.td
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HexagonSchedule.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonScheduleV5.td
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HexagonScheduleV55.td
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HexagonScheduleV60.td
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HexagonScheduleV62.td
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HexagonScheduleV65.td
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HexagonScheduleV66.td
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HexagonScheduleV67.td
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HexagonScheduleV67T.td
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HexagonScheduleV68.td [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
HexagonSelectionDAGInfo.cpp
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HexagonSelectionDAGInfo.h
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HexagonSplitConst32AndConst64.cpp
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HexagonSplitDouble.cpp [InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI) 2021-08-30 19:46:04 +02:00
HexagonStoreWidening.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
HexagonSubtarget.cpp [llvm] Use llvm::find (NFC) 2021-01-19 20:19:14 -08:00
HexagonSubtarget.h [Hexagon] Convert getTypeAlignment to return Align 2021-06-25 10:53:14 -05:00
HexagonTargetMachine.cpp [NFC] One more AttributeList::getAttribute(FunctionIndex) -> getFnAttr() 2021-08-13 16:56:42 -07:00
HexagonTargetMachine.h [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose 2021-05-07 21:51:47 -07:00
HexagonTargetObjectFile.cpp [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
HexagonTargetObjectFile.h
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HexagonTargetStreamer.h [MC] Add MCSubtargetInfo to MCAlignFragment 2021-09-07 15:46:19 +01:00
HexagonTargetTransformInfo.cpp [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when advising against unrolling due to a call in a loop 2021-08-03 00:57:26 +03:00
HexagonTargetTransformInfo.h [Target][CodeGen] Remove default CostKind arguments on inner/impl TTI overrides 2021-09-22 15:28:08 +01:00
HexagonVExtract.cpp
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HexagonVLIWPacketizer.cpp
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HexagonVLIWPacketizer.h
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HexagonVectorCombine.cpp [Hexagon] Use getTypeAllocSize to compute difference between objects 2021-09-13 19:04:59 -05:00
HexagonVectorLoopCarriedReuse.cpp
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HexagonVectorLoopCarriedReuse.h
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HexagonVectorPrint.cpp
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RDFCopy.cpp
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RDFCopy.h
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RDFDeadCode.cpp [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
RDFDeadCode.h
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