llvm-project/clang/test/CodeGen/RISCV
Zakk Chen d6a0560bf2 [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.
Demonstrate how to generate vadd/vfadd intrinsic functions

1. add -gen-riscv-vector-builtins for clang builtins.
2. add -gen-riscv-vector-builtin-codegen for clang codegen.
3. add -gen-riscv-vector-header for riscv_vector.h. It also generates
ifdef directives with extension checking, base on D94403.
4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h.
Generate overloading version Header for generic api.
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface
5. update tblgen doc for riscv related options.

riscv_vector.td also defines some unused type transformers for vadd,
because I think it could demonstrate how tranfer type work and we need
them for the whole intrinsic functions implementation in the future.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D95016
2021-03-10 18:43:43 -08:00
..
rvv-intrinsics [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. 2021-03-10 18:43:43 -08:00
rvv-intrinsics-generic [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. 2021-03-10 18:43:43 -08:00
riscv-atomics.c NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. 2021-02-11 17:35:09 -05:00
riscv-inline-asm.c
riscv-metadata.c
riscv-sdata-module-flag.c
riscv-v-debuginfo.c [Clang][RISCV] Define RISC-V V builtin types 2021-02-18 10:17:31 +08:00
riscv32-ilp32-abi.c
riscv32-ilp32-ilp32f-abi.c
riscv32-ilp32-ilp32f-ilp32d-abi.c
riscv32-ilp32d-abi.c
riscv32-ilp32f-abi.c
riscv32-ilp32f-ilp32d-abi.c
riscv64-lp64-abi.c
riscv64-lp64-lp64f-abi.c
riscv64-lp64-lp64f-lp64d-abi.c
riscv64-lp64d-abi.c
riscv64-lp64f-lp64d-abi.c