Luke d28297ff68 [RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector ... By implementing the method "unsigned RISCVTTIImpl::getRegisterBitWidth(bool Vector)", fixed-length vectorization is enabled when possible. Without this method, the "#pragma clang loop" directive is needed to enable vectorization(or the cost model may inform LLVM that "Vectorization is possible but not beneficial"). Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D97549		2021-03-05 10:54:51 +08:00
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lit.local.cfg	…
riscv-unroll.ll	[RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector	2021-03-05 10:54:51 +08:00
scalable-vf-hint.ll	…