llvm-project/llvm/lib/Transforms/InstCombine
Sanjay Patel a488c7879e [InstCombine] reduce signbit test of logic ops to cmp with zero
This is the pattern from the description of:
https://llvm.org/PR50816

There might be a way to generalize this to a smaller or more
generic pattern, but I have not found it yet.

https://alive2.llvm.org/ce/z/ShzJoF

define i1 @src(i8 %x) {
  %add = add i8 %x, -1
  %xor = xor i8 %x, -1
  %and = and i8 %add, %xor
  %r = icmp slt i8 %and, 0
  ret i1 %r
}

define i1 @tgt(i8 %x) {
  %r = icmp eq i8 %x, 0
  ret i1 %r
}
2021-07-12 09:01:26 -04:00
..
CMakeLists.txt llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
InstCombineAddSub.cpp [InstCombine] fix nsz (fast-math) propagation from fneg-of-select 2021-06-08 17:04:30 -04:00
InstCombineAndOrXor.cpp [InstCombine] InstCombinerImpl::visitOr - enable bitreverse matching 2021-05-15 13:39:09 +01:00
InstCombineAtomicRMW.cpp Add missing namespace closure comments. NFCI. 2020-09-23 16:19:25 +01:00
InstCombineCalls.cpp [InstCombine][NFC]Use only `replaceInstUsesWith`, NFC. 2021-07-08 13:58:30 -07:00
InstCombineCasts.cpp [InstCombine] Eliminate casts to optimize ctlz operation 2021-06-23 11:19:12 -04:00
InstCombineCompares.cpp [InstCombine] reduce signbit test of logic ops to cmp with zero 2021-07-12 09:01:26 -04:00
InstCombineInternal.h [InstCombine] Add optimization to prevent poison from being propagated. 2021-07-11 12:40:43 +09:00
InstCombineLoadStoreAlloca.cpp [InstCombine] Gracefully handle an alloca outside the alloca-AS 2021-06-29 09:38:13 -05:00
InstCombineMulDivRem.cpp [InstCombine] Fold (sext bool X) * (sext bool X) to zext (and X, X) 2021-06-18 16:28:06 +07:00
InstCombineNegator.cpp [Transforms] Use range-based for loops (NFC) 2021-02-08 22:33:53 -08:00
InstCombinePHI.cpp [InstCombine] Don't combine PHI before catchswitch 2021-07-02 12:10:24 -07:00
InstCombineSelect.cpp [InstCombine] avoid infinite loops with select folds of constant expressions 2021-06-20 09:46:25 -04:00
InstCombineShifts.cpp [InstCombine] fold shift-of-srem-by-2 to mask+shift 2021-04-20 17:10:16 -04:00
InstCombineSimplifyDemanded.cpp [InsCombine] Fix a few remaining vec transforms to use poison instead of undef 2021-05-31 18:47:09 +09:00
InstCombineVectorOps.cpp [NFC] Fix a few whitespace issues and typos. 2021-07-04 11:49:58 +01:00
InstructionCombining.cpp [InstCombine] Add optimization to prevent poison from being propagated. 2021-07-11 12:40:43 +09:00