Alex Bradbury 2146e8fb1e [RISCV] Constant materialisation for RV64I ... This commit introduces support for materialising 64-bit constants for RV64I, making use of the RISCVMatInt::generateInstSeq helper in order to share logic for immediate materialisation with the MC layer (where it's used for the li pseudoinstruction). test/CodeGen/RISCV/imm.ll is updated to test RV64, and gains new 64-bit constant tests. It would be preferable if anyext constant returns were sign rather than zero extended (see PR39092). This patch simply adds an explicit signext to the returns in imm.ll. Further optimisations for constant materialisation are possible, most notably for mask-like values which can be generated my loading -1 and shifting right. A future patch will standardise on the C++ codepath for immediate selection on RV32 as well as RV64, and then add further such optimisations to RISCVMatInt::generateInstSeq in order to benefit both RV32 and RV64 for codegen and li expansion. Differential Revision: https://reviews.llvm.org/D52962 llvm-svn: 347042		2018-11-16 10:14:16 +00:00
..
AsmParser	[RISCV] Introduce the RISCVMatInt::generateInstSeq helper	2018-11-15 10:11:31 +00:00
Disassembler	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
InstPrinter	[RISCV] Fix disassembling of fence instruction with invalid field	2018-10-11 22:49:13 +00:00
MCTargetDesc	[RISCV] Support .option relax and .option norelax	2018-11-12 14:25:07 +00:00
TargetInfo	Fix RISCV build after r318352	2017-11-16 18:39:31 +00:00
Utils	[RISCV] Introduce the RISCVMatInt::generateInstSeq helper	2018-11-15 10:11:31 +00:00
CMakeLists.txt	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
LLVMBuild.txt	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCV.h	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCV.td	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCVAsmPrinter.cpp	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVCallingConv.td	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVFrameLowering.cpp	[RISCV] Fix std::advance slowness	2018-08-24 23:13:59 +00:00
RISCVFrameLowering.h	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Constant materialisation for RV64I	2018-11-16 10:14:16 +00:00
RISCVISelLowering.cpp	[RISCV] Mark FREM as Expand	2018-11-15 14:46:11 +00:00
RISCVISelLowering.h	[RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}	2018-10-04 05:27:50 +00:00
RISCVInstrFormats.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp	[RISCV] Remove overzealous is64Bit checks	2018-10-04 14:30:03 +00:00
RISCVInstrInfo.h	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td	[RISCV] Avoid unnecessary XOR for seteq/setne 0	2018-11-09 14:47:36 +00:00
RISCVInstrInfoA.td	[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td	2018-10-03 11:14:26 +00:00
RISCVInstrInfoC.td	[RISCV] Mark C.EBREAK instruction as having side effects	2018-11-15 14:52:24 +00:00
RISCVInstrInfoD.td	[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32	2018-10-03 11:35:22 +00:00
RISCVInstrInfoF.td	[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32	2018-10-03 11:35:22 +00:00
RISCVInstrInfoM.td	[RISCV] Codegen support for the standard RV32M instruction set extension	2018-01-18 12:36:38 +00:00
RISCVMCInstLower.cpp	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv	2018-04-12 05:34:25 +00:00
RISCVMergeBaseOffset.cpp	Test commit.	2018-08-02 05:38:18 +00:00
RISCVRegisterInfo.cpp	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVSystemOperands.td	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCVTargetMachine.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00