llvm-project/llvm/test/CodeGen
Alex Bradbury 2146e8fb1e [RISCV] Constant materialisation for RV64I
This commit introduces support for materialising 64-bit constants for RV64I,
making use of the RISCVMatInt::generateInstSeq helper in order to share logic
for immediate materialisation with the MC layer (where it's used for the li
pseudoinstruction).

test/CodeGen/RISCV/imm.ll is updated to test RV64, and gains new 64-bit
constant tests. It would be preferable if anyext constant returns were sign
rather than zero extended (see PR39092). This patch simply adds an explicit
signext to the returns in imm.ll.

Further optimisations for constant materialisation are possible, most notably
for mask-like values which can be generated my loading -1 and shifting right.
A future patch will standardise on the C++ codepath for immediate selection on
RV32 as well as RV64, and then add further such optimisations to
RISCVMatInt::generateInstSeq in order to benefit both RV32 and RV64 for
codegen and li expansion.

Differential Revision: https://reviews.llvm.org/D52962

llvm-svn: 347042
2018-11-16 10:14:16 +00:00
..
AArch64 [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AMDGPU AMDGPU: Fix analyzeBranch failing with pseudoterminators 2018-11-16 05:03:02 +00:00
ARC
ARM [CodeGen] Fix forward scan in MachineBasicBlock::computeRegisterLiveness. 2018-11-14 00:39:29 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic [IR] Add a dedicated FNeg IR Instruction 2018-11-13 18:15:47 +00:00
Hexagon [Hexagon] Implement noreturn optimization 2018-11-09 18:16:24 +00:00
Inputs
Lanai
MIR [Power9] Allow gpr callee saved spills in prologue to vectors registers 2018-11-09 16:36:24 +00:00
MSP430 [MSP430] Add more tests for ABI and calling convention 2018-11-16 09:47:58 +00:00
Mips [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars 2018-11-09 18:04:34 +00:00
NVPTX
Nios2
PowerPC [PowerPC] Enhance the selection(ISD::VSELECT) of vector type 2018-11-14 02:34:45 +00:00
RISCV [RISCV] Constant materialisation for RV64I 2018-11-16 10:14:16 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SystemZ] Increase the number of VLREPs 2018-11-13 08:37:09 +00:00
Thumb [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] Split BBs after throw instructions 2018-11-16 00:47:18 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
X86 [X86] Add custom type legalization for v2i8/v4i8/v8i8 mul under -x86-experimental-vector-widening. 2018-11-16 06:15:21 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00