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OverMighty 232953f996 [AArch64] Add pattern for SQDML*Lv1i32_indexed 
There was no pattern to fold into these instructions. This patch adds
the pattern obtained from the following ACLE intrinsics so that they
generate sqdmlal/sqdmlsl instructions instead of separate sqdmull and
sqadd/sqsub instructions:
 - vqdmlalh_s16, vqdmlslh_s16
 - vqdmlalh_lane_s16, vqdmlalh_laneq_s16, vqdmlslh_lane_s16,
   vqdmlslh_laneq_s16 (when the lane index is 0)

It also modifies the result of the existing pattern for the latter, when
the lane index is not 0, to use the v1i32_indexed instructions instead
of the v4i16_indexed ones.

Fixes #49997.

Differential Revision: https://reviews.llvm.org/D131700
 		2022-08-17 12:00:47 +01:00
..
AsmParser [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
Disassembler [llvm] Qualify auto in range-based for loops (NFC) 2022-08-13 12:55:42 -07:00
GISel Revert "[AArch64][GlobalISel] Recognise some CCMPri" 2022-08-13 17:44:41 +01:00
MCTargetDesc [Target] Remove unused forward declarations (NFC) 2022-08-07 00:16:16 -07:00
TargetInfo
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Utils Revert "[AArch64] Add `foldCSELOfCSEl` DAG combine" 2022-08-16 20:29:37 -07:00
AArch64.h [CodeGen] Async unwind - add a pass to fix CFI information 2022-04-11 13:27:26 +01:00
AArch64.td [docs][AArch64] Label Features with Arm ARM Names 2022-08-09 18:45:50 +01:00
AArch64A53Fix835769.cpp Fix warnings about variables that are set but only used in debug mode 2022-04-06 10:01:46 +03:00
AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp Use drop_begin (NFC) 2022-07-31 15:17:09 -07:00
AArch64BranchTargets.cpp
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AArch64CallingConvention.cpp
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AArch64CallingConvention.h
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AArch64CallingConvention.td [AArch64] Treat x18 as callee-saved in functions with Windows calling convention on Darwin 2022-08-02 20:33:42 +03:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp [llvm] Call *set::insert without checking membership first (NFC) 2022-06-18 10:17:22 -07:00
AArch64Combine.td [AArch64][GlobalISel] Add undef combines to postlegalizer combiner. 2022-05-05 09:22:08 -07:00
AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64ConditionOptimizer.cpp
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AArch64ConditionalCompares.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64FalkorHWPFFix.cpp [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()) 2022-05-26 11:22:41 -07:00
AArch64FastISel.cpp [llvm] Qualify auto in range-based for loops (NFC) 2022-08-13 12:55:42 -07:00
AArch64FrameLowering.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64FrameLowering.h [Target] Remove unused forward declarations (NFC) 2022-08-07 00:16:16 -07:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64ISelLowering.cpp Revert "[AArch64] Add `foldCSELOfCSEl` DAG combine" 2022-08-16 20:29:37 -07:00
AArch64ISelLowering.h [AArch64] Add support for 256-bit non temporal loads 2022-08-16 12:19:36 +01:00
AArch64InstrAtomics.td GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD 2022-07-08 11:55:08 -04:00
AArch64InstrFormats.td [AArch64] Add pattern for SQDML*Lv1i32_indexed 2022-08-17 12:00:47 +01:00
AArch64InstrGISel.td
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AArch64InstrInfo.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64InstrInfo.h [MachineScheduler] Order more stores by ascending address 2022-06-13 17:33:50 +08:00
AArch64InstrInfo.td [AArch64] Add support for 256-bit non temporal loads 2022-08-16 12:19:36 +01:00
AArch64LoadStoreOptimizer.cpp [MachineScheduler] Order more stores by ascending address 2022-06-13 17:33:50 +08:00
AArch64LowerHomogeneousPrologEpilog.cpp
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AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64MIPeepholeOpt.cpp [llvm] Don't use Optional::getValue (NFC) 2022-06-20 22:45:45 -07:00
AArch64MachineFunctionInfo.cpp [llvm] Don't use Optional::hasValue (NFC) 2022-06-20 10:38:12 -07:00
AArch64MachineFunctionInfo.h [SVE][AArch64] Refine hasSVEArgsOrReturn 2022-07-01 13:24:55 +00:00
AArch64MachineScheduler.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64MachineScheduler.h [AArch64] Order STP Q's by ascending address 2022-05-23 09:50:44 +01:00
AArch64MacroFusion.cpp [AArch64] Split fuse-literals feature 2022-04-11 05:27:11 +00:00
AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h [AArch64] Teach perfect shuffles tables about D-lane movs 2022-05-17 18:16:45 +01:00
AArch64PfmCounters.td
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [AArch64] Treat x18 as callee-saved in functions with Windows calling convention on Darwin 2022-08-02 20:33:42 +03:00
AArch64RegisterInfo.h [SVE][AArch64] Refine hasSVEArgsOrReturn 2022-07-01 13:24:55 +00:00
AArch64RegisterInfo.td [AArch64] Make nxv1i1 types a legal type for SVE. 2022-07-01 15:11:13 +00:00
AArch64SIMDInstrOpt.cpp [llvm] Qualify auto in range-based for loops (NFC) 2022-08-13 12:55:42 -07:00
AArch64SLSHardening.cpp [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments 2022-03-16 20:25:42 +08:00
AArch64SMEInstrInfo.td [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics 2022-06-28 10:25:06 +01:00
AArch64SVEInstrInfo.td [AArch64][SVE] Add patterns to select masked FP arith 2022-08-08 08:44:13 +00:00
AArch64SchedA53.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedA55.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedA57.td [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex 2022-07-14 09:32:20 +00:00
AArch64SchedA57WriteRes.td
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AArch64SchedA64FX.td [AArch64] Fix and add A64FX scheduling resource/latency info 2022-08-09 10:53:40 +09:00
AArch64SchedAmpere1.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedCyclone.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedExynosM3.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedExynosM4.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedExynosM5.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedFalkor.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedKryoDetails.td
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AArch64SchedNeoverseN2.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedPredAmpere.td [AArch64] Support for Ampere1 core 2022-05-03 15:54:02 +01:00
AArch64SchedPredExynos.td [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates 2022-02-17 13:41:05 +03:00
AArch64SchedPredicates.td [AArch64] Support for Ampere1 core 2022-05-03 15:54:02 +01:00
AArch64SchedTSV110.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedThunderX.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedThunderX2T99.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64SchedThunderX3T110.td [AArch64] Initial sched model for Neoverse N2 2022-07-08 09:39:13 +00:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [clang] Add support for __builtin_memset_inline 2022-06-10 13:13:59 +00:00
AArch64SelectionDAGInfo.h [clang] Add support for __builtin_memset_inline 2022-06-10 13:13:59 +00:00
AArch64SpeculationHardening.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64StackTagging.cpp [MTE] [HWASan] Use LoopInfo for reachability queries. 2022-06-22 15:28:49 -07:00
AArch64StackTaggingPreRA.cpp Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options 2022-06-05 00:31:44 -07:00
AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp [AArch64] Add -aarch64-insert-extract-base-cost 2022-05-05 10:35:45 +00:00
AArch64Subtarget.h [AArch64] Add -aarch64-insert-extract-base-cost 2022-05-05 10:35:45 +00:00
AArch64SystemOperands.td [AArch64] Add target feature "all" 2022-06-30 10:37:58 -07:00
AArch64TargetMachine.cpp [AArch64] Move SeparateConstOffsetFromGEPPass before LSR and enable EnableGEPOpt by default. 2022-07-22 15:20:53 +01:00
AArch64TargetMachine.h mark getTargetTransformInfo and getTargetIRAnalysis as const 2022-02-25 14:30:44 -05:00
AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC 2022-08-08 11:24:15 -07:00
AArch64TargetTransformInfo.h [AArch64][LoopVectorize] Introduce trip count minimal value threshold to ignore tail-folding. 2022-08-09 22:10:17 +01:00
CMakeLists.txt [AArch64] Order STP Q's by ascending address 2022-05-23 09:50:44 +01:00
SMEInstrFormats.td [AArch64][SME] Add SME addha/va intrinsics 2022-07-05 09:47:17 +01:00
SVEInstrFormats.td [SVE] Expand DUPM patterns to handle all integer vector types. 2022-08-05 16:00:08 +00:00
SVEIntrinsicOpts.cpp [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00