..
arm64-atomic-128.ll
AArch64: use indivisible cmpxchg for 128-bit atomic loads at O0
2021-09-22 14:20:43 +01:00
arm64-atomic.ll
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
arm64-callingconv-ios.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
arm64-callingconv.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
arm64-fallback.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
arm64-irtranslator-fmuladd.ll
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arm64-irtranslator-gep.ll
[AArch64] Move SeparateConstOffsetFromGEPPass before LSR and enable EnableGEPOpt by default.
2022-07-22 15:20:53 +01:00
arm64-irtranslator-stackprotect.ll
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arm64-irtranslator-switch.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
arm64-irtranslator.ll
Untangle the mess which is MachineBasicBlock::hasAddressTaken().
2022-08-16 16:15:44 -07:00
arm64-regbankselect.mir
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artifact-combine-unmerge.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
artifact-find-value.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
assert-align.ll
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
2022-01-24 09:26:52 -05:00
builtin-return-address-pacret.ll
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byval-call.ll
[AArch64] Async unwind - function epilogues
2022-04-12 16:50:50 +01:00
call-lowering-const-bitcast-func.ll
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call-lowering-i128-on-stack.ll
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call-lowering-i256-crash.ll
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call-lowering-signext.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
call-lowering-sret-demotion.ll
[AArch64][GlobalISel] Add support for sret demotion.
2022-07-05 15:23:47 -07:00
call-lowering-vectors.ll
[AArch64][GlobalISel] Fix call lowering for <3 x i32> vector arguments
2022-07-08 10:25:45 +02:00
call-lowering-zeroext.ll
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call-translator-cse.ll
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call-translator-ios.ll
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call-translator-musttail.ll
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call-translator-tail-call-sret.ll
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call-translator-tail-call-weak.ll
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call-translator-tail-call.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
call-translator-variadic-musttail.ll
[AArch64] Order STP Q's by ascending address
2022-05-23 09:50:44 +01:00
call-translator.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
combine-add.mir
[GISel] Add new combines for G_ADD
2022-06-06 11:19:45 -07:00
combine-and-or-disjoint-mask.mir
Fix an or+and miscompile w/ GlobalISel
2022-05-18 19:09:47 -07:00
combine-anyext-crash.mir
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combine-build-vector.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-copy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-ext-debugloc.mir
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combine-ext.mir
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combine-extract-vec-elt.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-fabs.mir
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combine-fconstant.mir
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combine-flog2.mir
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combine-fminimum-fmaximum.mir
[GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM
2022-05-18 12:08:53 -07:00
combine-fminnum-fmaxnum.mir
[GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM
2022-05-18 12:08:53 -07:00
combine-fneg.mir
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combine-fptrunc.mir
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combine-fsqrt.mir
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combine-icmp-to-lhs-known-bits.mir
Add missing `REQUIRES: asserts` to combine-icmp-to-lhs-known-bits.mir
2021-09-03 09:25:37 -07:00
combine-insert-vec-elt.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-inttoptr-ptrtoint.mir
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combine-mul-to-shl.mir
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combine-mul.mir
[GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat vectors.
2021-09-30 14:31:25 -07:00
combine-mulo-with-2.mir
[GlobalISel] Combine mulo x, 2 -> addo x, x
2021-09-28 16:59:43 -07:00
combine-ptradd-int2ptr.mir
[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
2022-01-20 17:02:52 +00:00
combine-ptradd-reassociation.mir
[GlobalISel] Make G_PTR_ADD pattern matcher non-commutative.
2021-12-09 12:38:16 -08:00
combine-ptrtoint.mir
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combine-select.mir
[AArch64][GlobalISel] Implement combines for boolean G_SELECT->bitwise ops.
2022-02-20 00:53:09 -08:00
combine-sext-debugloc.mir
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combine-sext-trunc-sextload.mir
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combine-shift-immed-mismatch-crash.mir
[IR] Enable opaque pointers by default
2022-06-02 09:40:56 +02:00
combine-shift-of-shifted-dbg-value-fallback.ll
[GlobalISel][DebugInfo] Remove debug info with zero line from constants inserted at entry block
2022-07-25 17:19:01 +00:00
combine-shl.mir
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combine-trunc.mir
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combine-udiv.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
combine-udiv.mir
[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
2021-10-12 11:31:22 -07:00
combine-udivrem-use-bug.mir
[GlobalISel] Fix miscompile of G_UREM + G_UDIV due to not checking for equality
2022-07-25 16:03:05 -07:00
combine-umulh-to-lshr.mir
[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
2021-10-12 11:31:22 -07:00
combine-unmerge.mir
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combiner-load-store-indexing.ll
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constant-dbg-loc.ll
[GlobalISel][DebugInfo] Remove debug info with zero line from constants inserted at entry block
2022-07-25 17:19:01 +00:00
constant-mir-debugify.mir
[DIBuilder] Do not replace empty enum types
2021-08-30 12:33:03 -07:00
contract-store.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
darwin-tls-call-clobber.ll
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debug-cpp.ll
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debug-insts.ll
[GlobalISel] Handle nullptr constants in dbg.value
2022-07-28 14:58:14 -07:00
debug-loc-legalize-tail-call.mir
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dynamic-alloca-lifetime.ll
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dynamic-alloca.ll
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fallback-nofastisel.ll
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fconstant-dbg-loc.ll
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fold-brcond-fcmp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
fold-fp-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
fold-global-offsets-target-features.mir
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fold-global-offsets.mir
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fold-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
form-bitfield-extract-from-and.mir
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form-bitfield-extract-from-sextinreg.mir
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form-bitfield-extract-from-shr-and.mir
Fix zero-width bitfield extracts to emit 0
2022-05-03 14:46:42 -07:00
form-bitfield-extract-from-shr.mir
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fp16-copy-gpr.mir
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fp128-legalize-crash-pr35690.mir
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freeze.ll
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gisel-abort.ll
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gisel-commandline-option-fastisel.ll
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gisel-commandline-option.ll
CodeGen: Remove AliasAnalysis from regalloc
2022-07-18 17:23:41 -04:00
gisel-fail-intermediate-legalizer.ll
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huge-switch.ll
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
implicit_def_rbs_crash.mir
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inline-asm.ll
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inline-memcpy-forced.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memcpy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memmove.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memset.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-small-memcpy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
integration-shuffle-vector.ll
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inttoptr_add.ll
[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
2022-01-20 17:02:52 +00:00
irtranslator-arguments.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
irtranslator-atomic-metadata.ll
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irtranslator-bitcast.ll
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irtranslator-block-order.ll
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irtranslator-condbr-lower-tree.ll
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irtranslator-convert-fp16-intrinsics.ll
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irtranslator-delayed-stack-protector.ll
Revert "[GISel] Unify use of getStackGuard"
2022-07-12 17:00:43 -04:00
irtranslator-dilocation.ll
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irtranslator-duplicate-types-param.ll
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irtranslator-exceptions.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
irtranslator-extends.ll
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irtranslator-extract-used-by-dbg.ll
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irtranslator-fixed-point-intrinsics.ll
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irtranslator-fp-min-max-intrinsics.ll
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irtranslator-indirect-br-repeated-block.ll
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irtranslator-inline-asm.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
irtranslator-invoke-probabilities.ll
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irtranslator-load-metadata.ll
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irtranslator-localescape.ll
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irtranslator-max-address-space.ll
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irtranslator-memcpy-inline.ll
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irtranslator-memfunc-undef.ll
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irtranslator-no-op-intrinsics.ll
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irtranslator-no-unwind-inline-asm.ll
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irtranslator-one-by-n-vector-ptr-add.ll
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irtranslator-reductions.ll
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irtranslator-split-vector-arg.ll
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irtranslator-stack-evt-bug47619.ll
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irtranslator-stack-objects.ll
[CallLowering] Support opaque pointers
2021-09-10 18:32:12 +02:00
irtranslator-stack-protector-windows.ll
[GlobalIsel] Fix fallback if stack protector isn't supported.
2022-05-13 14:17:27 -07:00
irtranslator-store-metadata.ll
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irtranslator-switch-bittest.ll
[GlobalISel][IRTranslator] Fix crash during bit-test switch optimization with odd types.
2021-09-24 00:19:27 -07:00
irtranslator-tbaa.ll
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irtranslator-unreachable.ll
Revert "Revert "[GlobalISel][IRTranslator] Emit trap intrinsic for "unreachable"""
2021-10-06 04:16:19 -07:00
irtranslator-unwind-inline-asm.ll
[GlobalISel] Ensure that translateInvoke adds all successors for inlineasm
2021-11-09 16:20:34 -08:00
irtranslator-volatile-load-pr36018.ll
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irtranslator-weird-alloca-size.ll
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labels-are-not-dead.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-abs.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-add.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-and.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-atomicrmw.mir
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legalize-bitreverse.mir
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legalize-blockaddress.mir
Untangle the mess which is MachineBasicBlock::hasAddressTaken().
2022-08-16 16:15:44 -07:00
legalize-bswap.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-build-vector.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-bzero-unsupported.mir
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legalize-bzero.mir
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legalize-ceil.mir
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legalize-cmp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-cmpxchg-128.mir
AArch64: do not use xzr for ldxp -> stxp dataflow.
2022-02-09 12:29:16 +00:00
legalize-cmpxchg-with-success.mir
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legalize-cmpxchg.mir
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legalize-combines.mir
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legalize-concat-vectors.mir
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legalize-constant.mir
[GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT.
2022-07-14 11:05:10 -07:00
legalize-cos.mir
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legalize-ctlz.mir
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legalize-ctpop-no-implicit-float.mir
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legalize-ctpop.mir
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legalize-cttz-zero-undef.mir
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legalize-cttz.mir
[AArch64][GlobalISel] Lower vector G_CTTZ.
2022-07-27 00:14:30 -07:00
legalize-div.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-divrem.mir
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legalize-dyn-alloca.mir
…
legalize-exceptions.ll
…
legalize-exp.mir
…
legalize-ext-cse.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ext-csedebug-output.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-extload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-extract-vector-elt.mir
[GlobalISel] Widen G_EXTRACT_VECTOR_ELT using anyext instead of sext.
2021-10-04 12:19:19 -07:00
legalize-extracts.mir
[GlobalISel] NFC: Add test coverage for s144 and s142
2022-04-05 15:26:46 -07:00
legalize-fcmp.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fexp2.mir
…
legalize-fma.mir
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legalize-fmaximum.mir
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
2021-12-09 11:54:14 -08:00
legalize-fmaxnum.mir
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legalize-fminimum.mir
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
2021-12-09 11:54:14 -08:00
legalize-fminnum.mir
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legalize-fp-arith-fp16.mir
[AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
2021-08-24 13:54:28 -07:00
legalize-fp-arith.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fp16-fconstant.mir
[GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT.
2022-07-14 11:05:10 -07:00
legalize-fp128-fconstant.mir
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legalize-fpext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fptoi.mir
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legalize-fptrunc.mir
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legalize-freeze.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-frint.mir
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legalize-fshl.mir
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legalize-fshr.mir
…
legalize-global-pic.mir
…
legalize-global.mir
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legalize-ignore-hint.mir
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legalize-ignore-non-generic.mir
…
legalize-insert-vector-elt.mir
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legalize-inserts.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-intrinsic-get-dynamic-area-offset.mir
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legalize-intrinsic-min-max.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-intrinsic-round.mir
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legalize-intrinsic-trunc.mir
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legalize-inttoptr-xfail-1.mir
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legalize-inttoptr-xfail-2.mir
…
legalize-inttoptr.mir
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legalize-itofp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-llround.mir
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legalize-load-store-fewerElts.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-store-vector-of-ptr-debugloc.mir
…
legalize-load-store-vector-of-ptr.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-store.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-trunc.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-log.mir
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legalize-log2.mir
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legalize-log10.mir
…
legalize-lrint.mir
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legalize-lround.mir
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legalize-memcpy-et-al.mir
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legalize-memcpy-with-debug-info.mir
[llvm] Inclusive language: replace master with main in file paths in LIT tests
2021-11-08 12:39:50 -06:00
legalize-memlib-debug-loc.mir
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legalize-merge-values.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-min-max.mir
…
legalize-mul.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-nearbyint.mir
…
legalize-non-pow2-load-store.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-or.mir
[GlobalISel] NFC: Regen some tests + improve test coverage for wide even types
2022-04-05 12:13:22 -07:00
legalize-phi-insertpt-decrement.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-phi.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-pow.mir
…
legalize-property.mir
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legalize-ptr-add.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ptrtoint.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-add.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-and.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-fadd.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-or.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-xor.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-rem.mir
AArch64/GlobalISel: Remove pointless s1 legalize rules
2022-04-12 16:54:04 -04:00
legalize-rotr-rotl.mir
[AArch64][GlobalISel] Fix custom legalization of rotates using sext for shift vs zext.
2022-07-27 22:10:42 -07:00
legalize-s128-div.mir
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
legalize-sadde.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-saddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-saddsat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sbfx.mir
…
legalize-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sext-128.ll
…
legalize-sext-128.mir
…
legalize-sext-copy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sext-zext-128.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sextload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-shift-imm-promote-dloc.mir
…
legalize-shift.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-shuffle-vector.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-simple.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sin.mir
…
legalize-sqrt.mir
…
legalize-ssube.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ssubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ssubsat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sub.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uadd-sat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uadde.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uaddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ubfx.mir
…
legalize-undef.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-unmerge-values.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-usub-sat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-usube.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-usubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-vaarg.mir
…
legalize-vacopy.mir
…
legalize-vector-cmp.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-vector-shift.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-xor.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-zextload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalizer-combiner-zext-trunc-crash.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalizer-combiner.mir
…
legalizer-info-validation.mir
Replace hard coded number with regex so the test passes on downstream projects that may define additional opcodes.
2022-07-08 15:49:37 -07:00
lifetime-marker-no-dce.mir
…
load-addressing-modes.mir
…
load-wro-addressing-modes.mir
…
localizer-arm64-tti.ll
[AArch64][GlobalISel] Add heuristics for localizing G_CONSTANT.
2022-07-27 10:51:16 -07:00
localizer-in-O0-pipeline.mir
…
localizer.mir
…
lower-neon-vector-fcmp.mir
…
machine-cse-mid-pipeline.mir
…
memcpy_chk_no_tail.ll
…
merge-stores-truncating.ll
[AArch64][GlobalISel] combine and + [la]sr => ubfx
2021-10-18 10:33:01 -07:00
merge-stores-truncating.mir
[GlobalISel] Fix the stores of truncates -> wide store combine for non-evenly dividing type sizes.
2021-10-09 21:18:20 -07:00
no-neon-no-fp.ll
…
no-regclass.mir
…
non-pow-2-extload-combine.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
observer-change-crash.mir
…
opt-and-tbnz-tbz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-and-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-compare.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-ext-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-shift-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-trunc-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-xor-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-overlapping-and-postlegalize.mir
[AArch64][GlobalISel] Run overlapping_and after legalization
2021-09-28 17:13:34 -07:00
opt-overlapping-and.mir
…
opt-shifted-reg-compare.mir
…
phi-mir-debugify.mir
[DIBuilder] Do not replace empty enum types
2021-08-30 12:33:03 -07:00
postlegalizer-combine-ptr-add-chain.mir
…
postlegalizer-combiner-and-trivial-mask.mir
…
postlegalizer-combiner-anyext-to-zext.mir
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
2021-10-01 15:01:20 -07:00
postlegalizer-combiner-constant-fold.mir
…
postlegalizer-combiner-copy-prop.mir
…
postlegalizer-combiner-identity.mir
…
postlegalizer-combiner-merge.mir
…
postlegalizer-combiner-redundant-sextinreg.mir
…
postlegalizer-combiner-split-zero-stores.mir
AArch64/GlobalISel: Fix memory type in test
2021-12-20 19:11:48 -05:00
postlegalizer-combiner-undef.mir
[AArch64][GlobalISel] Add undef combines to postlegalizer combiner.
2022-05-05 09:22:08 -07:00
postlegalizer-lowering-adjust-icmp-imm.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
postlegalizer-lowering-build-vector-to-dup.mir
…
postlegalizer-lowering-ext.mir
…
postlegalizer-lowering-rev.mir
…
postlegalizer-lowering-shuf-to-ins.mir
…
postlegalizer-lowering-shuffle-duplane.mir
…
postlegalizer-lowering-shuffle-splat.mir
…
postlegalizer-lowering-swap-compare-operands.mir
…
postlegalizer-lowering-trn.mir
…
postlegalizer-lowering-truncstore.mir
…
postlegalizer-lowering-uzp.mir
…
postlegalizer-lowering-vashr-vlshr.mir
…
postlegalizer-lowering-zip.mir
…
postlegalizercombiner-extending-loads.mir
…
postlegalizercombiner-extractvec-faddp.mir
…
postlegalizercombiner-hoist-same-hands.mir
…
postlegalizercombiner-mulpow2.mir
…
postlegalizercombiner-rotate.mir
[GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero
2021-09-08 10:09:02 -07:00
postlegalizercombiner-select.mir
…
postselectopt-constrain-new-regop.mir
…
postselectopt-dead-cc-defs-in-fcmp.mir
…
prelegalizer-combiner-addo-zero.mir
[GlobalISel] Combine (G_*ADDO x, 0) -> x + no carry out
2022-02-03 14:25:15 -08:00
prelegalizer-combiner-divrem-insertpt-crash.mir
…
prelegalizer-combiner-icmp-to-true-false-known-bits.mir
…
prelegalizer-combiner-load-and-mask.mir
[GlobalISel] Fix and(load)->zextload combine crash.
2022-07-13 14:58:45 -07:00
prelegalizer-combiner-load-or-pattern-align.mir
…
prelegalizer-combiner-load-or-pattern.mir
…
prelegalizer-combiner-mulo-zero.mir
[GlobalISel] Combine: (G_*MULO x, 0) -> 0 + no carry out
2022-02-03 14:23:58 -08:00
prelegalizer-combiner-narrow-binop-feeding-add.mir
…
prelegalizercombiner-ashr-shl-to-sext-inreg.mir
…
prelegalizercombiner-binop-same-val.mir
…
prelegalizercombiner-br.mir
…
prelegalizercombiner-bzero.mir
…
prelegalizercombiner-concat-vectors.mir
…
prelegalizercombiner-copy-prop-disabled.mir
…
prelegalizercombiner-extending-loads-cornercases.mir
…
prelegalizercombiner-extending-loads-s1.mir
…
prelegalizercombiner-extending-loads.mir
…
prelegalizercombiner-funnel-shifts-to-rotates.mir
…
prelegalizercombiner-hoist-same-hands.mir
…
prelegalizercombiner-icmp-redundant-trunc.mir
…
prelegalizercombiner-invert-cmp.mir
…
prelegalizercombiner-not-really-equiv-insts.mir
[GlobalISel] Don't combine instructions which are fed by memory instructions using different size
2022-02-04 15:00:47 -08:00
prelegalizercombiner-prop-extends-phi.mir
…
prelegalizercombiner-ptradd-chain.mir
…
prelegalizercombiner-select.mir
…
prelegalizercombiner-sextload-from-sextinreg.mir
…
prelegalizercombiner-shuffle-vector.mir
…
prelegalizercombiner-simplify-add.mir
…
prelegalizercombiner-trivial-arith.mir
[AArch64][GlobalISel] Fix combiner assertion in matchConstantOp().
2021-10-11 15:55:13 -07:00
prelegalizercombiner-undef.mir
[GlobalISel] Combine G_SHL, G_ASHR, G_SHL of undef shifts to undef.
2022-05-13 12:20:34 -07:00
prelegalizercombiner-xor-of-and-with-same-reg.mir
…
preselect-process-phis.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
rbs-matrixindex-regclass-crash.mir
[AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added.
2021-10-29 11:47:00 -07:00
reg-bank-128bit.mir
…
regbank-assert-align.mir
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
2022-01-24 09:26:52 -05:00
regbank-assert-sext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-assert-zext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-ceil.mir
…
regbank-dup.mir
…
regbank-extract-vector-elt.mir
…
regbank-extract.mir
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
regbank-fcmp.mir
…
regbank-fma.mir
…
regbank-fmaximum.mir
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
2021-12-09 12:52:32 -08:00
regbank-fminimum.mir
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
2021-12-09 12:52:32 -08:00
regbank-fp-use-def.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-inlineasm.mir
…
regbank-insert-vector-elt.mir
…
regbank-intrinsic-round.mir
…
regbank-intrinsic-trunc.mir
…
regbank-intrinsic.mir
…
regbank-llround.mir
…
regbank-lround.mir
…
regbank-maxnum.mir
…
regbank-minnum.mir
…
regbank-nearbyint.mir
…
regbank-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-shift-imm-64.mir
…
regbank-trunc-s128.mir
…
regbankselect-build-vector.mir
…
regbankselect-dbg-value.mir
…
regbankselect-default.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbankselect-reductions.mir
…
regbankselect-reg_sequence.mir
…
regbankselect-unmerge-vec.mir
…
ret-1x-vec.ll
…
ret-vec-promote.ll
…
retry-artifact-combine.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
salvage-debug-info-dead.mir
[GlobalISel][DebugInfo] salvageDebugInfo analogue for gMIR
2022-08-01 11:14:53 +02:00
select-abs.mir
…
select-add-low.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
select-arith-extended-reg.mir
…
select-arith-shifted-reg.mir
…
select-atomic-load-store.mir
…
select-atomicrmw.mir
…
select-binop.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-bitcast-bigendian.mir
…
select-bitcast.mir
…
select-bitfield-insert.ll
…
select-bitreverse.mir
…
select-blockaddress.mir
Untangle the mess which is MachineBasicBlock::hasAddressTaken().
2022-08-16 16:15:44 -07:00
select-br.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-brcond-of-binop.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-bswap.mir
…
select-build-vector.mir
[AArch64][GlobalISel] Optimize G_BUILD_VECTOR of undef + 1 elt -> SUBREG_TO_REG
2021-08-26 11:45:11 -07:00
select-cbz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ceil.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-cmp.mir
[AArch64][GlobalISel] Fold 64-bit cmps with 64-bit adds
2021-10-21 13:51:44 -07:00
select-cmpxchg.mir
…
select-concat-vectors.mir
…
select-const-pool.mir
…
select-const-vector.mir
…
select-constant.mir
…
select-ctlz.mir
…
select-ctpop.mir
…
select-dbg-value.mir
[globalisel] Select register bank for DBG_VALUE
2022-08-09 13:11:51 +08:00
select-dup.mir
…
select-ext.mir
…
select-extload.mir
…
select-extract-vector-elt-with-extend.mir
[AArch64][GlobalISel] Fix crash in the extend(extract_vector_elt) optimization.
2021-09-23 23:07:16 -07:00
select-extract-vector-elt.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-extract.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-fabs.mir
…
select-faddp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fcmp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-floor.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fma.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fmaximum.mir
[GlobalISel] Import patterns for G_FMAXIMUM + G_FMINIMUM
2022-07-26 10:58:44 -07:00
select-fminimum.mir
[GlobalISel] Import patterns for G_FMAXIMUM + G_FMINIMUM
2022-07-26 10:58:44 -07:00
select-fmul-indexed.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fp-casts.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fp16-fconstant.mir
[AArch64][GlobalISel] Select full-fp16 s16 G_FCONSTANT as a constant pool load
2021-09-10 19:36:34 -07:00
select-frameaddr.ll
…
select-frint-nofp16.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-frint.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-gv-cmodel-large.mir
…
select-gv-cmodel-tiny.mir
…
select-gv-with-offset.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
select-hint.mir
[globalisel] Select register bank for DBG_VALUE
2022-08-09 13:11:51 +08:00
select-imm.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-implicit-def.mir
…
select-insert-extract.mir
…
select-insert-vector-elt.mir
…
select-int-ext.mir
…
select-int-ptr-casts.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-intrinsic-aarch64-hint.mir
…
select-intrinsic-aarch64-sdiv.mir
…
select-intrinsic-crypto-aesmc.mir
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
select-intrinsic-round.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-intrinsic-trunc.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-intrinsic-uaddlv.mir
…
select-jump-table-brjt-constrain.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-jump-table-brjt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ld2.mir
…
select-ld4.mir
…
select-ldaxr-intrin.mir
…
select-ldxr-intrin.mir
…
select-load-store-vector-of-ptr.mir
…
select-load.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-logical-imm.mir
…
select-logical-shifted-reg.mir
…
select-mul.mir
[AArch64][GlobalISel] Add selection tests for vector G_UMULH/G_SMULH.
2021-09-29 02:55:08 -07:00
select-muladd.mir
…
select-nearbyint.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-neon-vcvtfxu2fp.mir
…
select-neon-vector-fcmp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-phi.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-pr32733.mir
…
select-property.mir
…
select-ptr-add.mir
…
select-reduce-add.mir
…
select-reduce-fadd.mir
…
select-redundant-zext-of-load.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-redundant-zext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-returnaddr.ll
…
select-returnaddress-liveins.mir
…
select-rev.mir
…
select-rotate.mir
[AArch64][GlobalISel] Support for folding G_ROTR as shifted operands.
2021-09-02 21:37:24 -07:00
select-saddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-sbfx.mir
…
select-scalar-merge.mir
…
select-scalar-shift-imm.mir
AArch64 GIsel: legalize lshr operands, even if it is poison
2021-11-30 15:28:35 -05:00
select-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-sextload.mir
…
select-shuffle-vector.mir
…
select-shufflevec-undef-mask-elt.mir
…
select-sqrt.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-ssubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-st2.mir
…
select-static.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-stlxr-intrin.mir
…
select-store-truncating-float.mir
[AArch64][GlobalISel] Fix incorrect handling of fp truncating stores.
2021-08-24 16:07:00 -07:00
select-store.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-stx.mir
…
select-trap.mir
…
select-trn.mir
…
select-trunc.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-truncstore-atomic.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-uaddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ubfx.mir
…
select-unmerge.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-unreachable-blocks.mir
[GlobalISel] Clear unreachable blocks' contents after selection.
2021-10-05 23:06:22 -07:00
select-usubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-uzp.mir
…
select-vector-icmp.mir
…
select-vector-shift.mir
…
select-with-no-legality-check.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-xor.mir
…
select-zext-as-copy.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-zextload.mir
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
2022-07-08 11:55:08 -04:00
select-zip.mir
…
select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
sext-inreg-ldrow-16b.mir
…
speculative-hardening-brcond.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
store-addressing-modes.mir
…
store-merging.ll
[GlobalISel] Fix store merging incorrectly merging volatile stores.
2022-03-14 13:48:51 -07:00
store-merging.mir
[GlobalISel] Add a store-merging optimization pass and enable for AArch64.
2021-11-15 21:10:39 -08:00
store-wro-addressing-modes.mir
…
subreg-copy.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
swifterror.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
swiftself.ll
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00
tail-call-no-save-fp-lr.ll
…
tbnz-slt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
tbz-sgt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
translate-constant-dag.ll
…
translate-gep.ll
…
translate-ret.ll
…
uaddo-8-16-bits.mir
[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.
2021-12-05 15:55:59 -05:00
ubsantrap.ll
…
unknown-intrinsic.ll
…
unwind-inline-asm.ll
…
v8.4-atomic-128.ll
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
2021-09-20 09:50:11 +01:00
varargs-ios-translator.ll
…
vastart.ll
…
vec-s16-param.ll
…
widen-narrow-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
xro-addressing-mode-constant.mir
…
