130 lines
3.3 KiB
YAML
130 lines
3.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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---
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name: add_lhs_sub_reg
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: add_lhs_sub_reg
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SUB %0, %1
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%3:_(s32) = G_ADD %2, %1
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$w0 = COPY %3
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...
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---
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name: add_lhs_sub_reg_wide
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: add_lhs_sub_reg_wide
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
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; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
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%0:_(s128) = COPY $q0
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%1:_(s128) = COPY $q1
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%2:_(s128) = G_SUB %0, %1
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%3:_(s128) = G_ADD %2, %1
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$q0 = COPY %3
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...
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---
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name: add_lhs_sub_reg_vec
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: add_lhs_sub_reg_vec
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
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; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
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%0:_(<4 x s16>) = COPY $x0
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%1:_(<4 x s16>) = COPY $x1
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%2:_(<4 x s16>) = G_SUB %0, %1
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%3:_(<4 x s16>) = G_ADD %2, %1
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$x0 = COPY %3
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...
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---
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name: add_rhs_sub_reg
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: add_rhs_sub_reg
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SUB %0, %1
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%3:_(s32) = G_ADD %1, %2
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$w0 = COPY %3
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...
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---
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name: add_rhs_sub_reg_wide
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: add_rhs_sub_reg_wide
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
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; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
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%0:_(s128) = COPY $q0
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%1:_(s128) = COPY $q1
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%2:_(s128) = G_SUB %0, %1
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%3:_(s128) = G_ADD %1, %2
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$q0 = COPY %3
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...
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---
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name: add_rhs_sub_reg_vec
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: add_rhs_sub_reg_vec
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
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; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
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%0:_(<4 x s16>) = COPY $x0
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%1:_(<4 x s16>) = COPY $x1
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%2:_(<4 x s16>) = G_SUB %0, %1
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%3:_(<4 x s16>) = G_ADD %1, %2
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$x0 = COPY %3
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...
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