173 lines
7.4 KiB
LLVM
173 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX10
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX10
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX11
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define i32 @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: global_atomic_csub:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
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ret i32 %ret
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}
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define i32 @global_atomic_csub_offset(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub_offset:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_mov_b64 s[4:5], 0x1000
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; GFX10-NEXT: v_mov_b32_e32 v3, s4
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; GFX10-NEXT: v_mov_b32_e32 v4, s5
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; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
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; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
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; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: global_atomic_csub_offset:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: s_mov_b64 s[0:1], 0x1000
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
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; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
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; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
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ret i32 %ret
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}
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define void @global_atomic_csub_nortn(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub_nortn:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: global_atomic_csub_nortn:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
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ret void
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}
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define void @global_atomic_csub_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub_offset_nortn:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_mov_b64 s[4:5], 0x1000
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; GFX10-NEXT: v_mov_b32_e32 v3, s4
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; GFX10-NEXT: v_mov_b32_e32 v4, s5
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; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
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; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
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; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: global_atomic_csub_offset_nortn:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: s_mov_b64 s[0:1], 0x1000
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
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; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
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; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
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ret void
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}
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define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub_sgpr_base_offset:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v1, 0x1000
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: global_atomic_csub_sgpr_base_offset:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v1, 0x1000 :: v_dual_mov_b32 v0, s2
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; GFX11-NEXT: global_atomic_csub_u32 v0, v1, v0, s[0:1] glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: global_store_b32 v[0:1], v0, off
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
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store i32 %ret, i32 addrspace(1)* undef
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ret void
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}
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define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
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; GFX10-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v1, 0x1000
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v1, 0x1000 :: v_dual_mov_b32 v0, s2
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; GFX11-NEXT: global_atomic_csub_u32 v0, v1, v0, s[0:1] glc
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
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%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
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ret void
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}
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declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1
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attributes #0 = { nounwind willreturn }
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attributes #1 = { argmemonly nounwind }
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