446 lines
14 KiB
YAML
446 lines
14 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
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--- |
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define amdgpu_ps void @test_strict_wwm_scc() {
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ret void
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}
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define amdgpu_ps void @test_strict_wwm_scc2() {
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ret void
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}
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define amdgpu_ps void @no_cfg() {
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ret void
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}
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define amdgpu_ps void @copy_exec() {
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ret void
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}
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define amdgpu_ps void @scc_always_live() {
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ret void
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}
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define amdgpu_ps void @test_wwm_set_inactive_propagation() {
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ret void
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}
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define amdgpu_ps void @test_wqm_lr_phi() {
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ret void
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}
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define amdgpu_cs void @no_wqm_in_cs() {
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ret void
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}
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define amdgpu_es void @no_wqm_in_es() {
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ret void
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}
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define amdgpu_gs void @no_wqm_in_gs() {
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ret void
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}
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define amdgpu_hs void @no_wqm_in_hs() {
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ret void
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}
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define amdgpu_ls void @no_wqm_in_ls() {
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ret void
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}
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define amdgpu_vs void @no_wqm_in_vs() {
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ret void
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}
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...
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---
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---
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# Check for awareness that s_or_saveexec_b64 clobbers SCC
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#
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#CHECK: ENTER_STRICT_WWM
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#CHECK: S_CMP_LT_I32
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#CHECK: S_CSELECT_B32
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name: test_strict_wwm_scc
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_32, preferred-register: '' }
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- { id: 1, class: sgpr_32, preferred-register: '' }
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- { id: 2, class: sgpr_32, preferred-register: '' }
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- { id: 3, class: vgpr_32, preferred-register: '' }
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- { id: 4, class: vgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_32, preferred-register: '' }
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- { id: 6, class: vgpr_32, preferred-register: '' }
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- { id: 7, class: vgpr_32, preferred-register: '' }
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- { id: 8, class: sreg_32_xm0, preferred-register: '' }
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- { id: 9, class: sreg_32, preferred-register: '' }
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- { id: 10, class: sreg_32, preferred-register: '' }
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- { id: 11, class: vgpr_32, preferred-register: '' }
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- { id: 12, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$sgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr1', virtual-reg: '%1' }
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- { reg: '$sgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr0', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%3 = COPY $vgpr0
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%2 = COPY $sgpr2
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%1 = COPY $sgpr1
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%0 = COPY $sgpr0
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S_CMP_LT_I32 0, %0, implicit-def $scc
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%12 = V_ADD_CO_U32_e32 %3, %3, implicit-def $vcc, implicit $exec
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%5 = S_CSELECT_B32 %2, %1, implicit $scc
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%11 = V_ADD_CO_U32_e32 %5, %12, implicit-def $vcc, implicit $exec
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$vgpr0 = STRICT_WWM %11, implicit $exec
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SI_RETURN_TO_EPILOG $vgpr0
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...
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---
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# Second test for awareness that s_or_saveexec_b64 clobbers SCC
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# Because entry block is treated differently.
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#
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#CHECK: %bb.1
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#CHECK: S_CMP_LT_I32
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#CHECK: COPY $scc
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#CHECK: ENTER_STRICT_WWM
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#CHECK: $scc = COPY
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#CHECK: S_CSELECT_B32
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name: test_strict_wwm_scc2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%3:vgpr_32 = COPY $vgpr0
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%13:sgpr_128 = IMPLICIT_DEF
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bb.1:
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S_CMP_LT_I32 0, %0:sgpr_32, implicit-def $scc
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%10:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %3:vgpr_32, %13:sgpr_128, 0, 0, 0, 0, 0, implicit $exec
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%12:vgpr_32 = V_ADD_CO_U32_e32 %3:vgpr_32, %3:vgpr_32, implicit-def $vcc, implicit $exec
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%5:sgpr_32 = S_CSELECT_B32 %2:sgpr_32, %1:sgpr_32, implicit $scc
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%11:vgpr_32 = V_ADD_CO_U32_e32 %5:sgpr_32, %12:vgpr_32, implicit-def $vcc, implicit $exec
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$vgpr0 = STRICT_WWM %11:vgpr_32, implicit $exec
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$vgpr1 = COPY %10:vgpr_32
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SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
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...
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---
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# V_SET_INACTIVE, when its second operand is undef, is replaced by a
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# COPY by si-wqm. Ensure the instruction is removed.
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#CHECK-NOT: V_SET_INACTIVE
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name: no_cfg
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: sgpr_32, preferred-register: '' }
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- { id: 1, class: sgpr_32, preferred-register: '' }
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- { id: 2, class: sgpr_32, preferred-register: '' }
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- { id: 3, class: sgpr_32, preferred-register: '' }
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- { id: 4, class: sgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_128, preferred-register: '' }
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- { id: 6, class: sgpr_128, preferred-register: '' }
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- { id: 7, class: sreg_32, preferred-register: '' }
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- { id: 8, class: vreg_64, preferred-register: '' }
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- { id: 9, class: sreg_32, preferred-register: '' }
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- { id: 10, class: vgpr_32, preferred-register: '' }
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- { id: 11, class: vgpr_32, preferred-register: '' }
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- { id: 12, class: sreg_32, preferred-register: '' }
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- { id: 13, class: vgpr_32, preferred-register: '' }
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- { id: 14, class: vgpr_32, preferred-register: '' }
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- { id: 15, class: vgpr_32, preferred-register: '' }
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- { id: 16, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$sgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr1', virtual-reg: '%1' }
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- { reg: '$sgpr2', virtual-reg: '%2' }
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- { reg: '$sgpr3', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:sgpr_128 = COPY %6
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%7:sreg_32 = S_MOV_B32 0
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%8:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %6, %7, 0, 0, 0, 0, implicit $exec
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%16:vgpr_32 = COPY %8.sub1
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%11:vgpr_32 = COPY %16
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%10:vgpr_32 = V_SET_INACTIVE_B32 %11, undef %12:sreg_32, implicit $exec, implicit-def $scc
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%14:vgpr_32 = COPY %7
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%13:vgpr_32 = V_MOV_B32_dpp %14, killed %10, 323, 12, 15, 0, implicit $exec
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early-clobber %15:vgpr_32 = STRICT_WWM killed %13, implicit $exec
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BUFFER_STORE_DWORD_OFFSET_exact killed %15, %6, %7, 4, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# Ensure that strict_wwm is not put around an EXEC copy
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#CHECK-LABEL: name: copy_exec
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#CHECK: %7:sreg_64 = COPY $exec
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#CHECK-NEXT: %14:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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#CHECK-NEXT: %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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#CHECK-NEXT: $exec = EXIT_STRICT_WWM %14
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#CHECK-NEXT: %9:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %7.sub0, 0, implicit $exec
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name: copy_exec
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:sreg_32 = S_MOV_B32 0
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%6:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %4, %5, 0, 0, 0, 0, implicit $exec
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%8:sreg_64 = COPY $exec
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%9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec
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%11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
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%12:sreg_32 = V_READLANE_B32 %11:vgpr_32, 63
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early-clobber %13:sreg_32 = STRICT_WWM %9:vgpr_32, implicit $exec
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%14:vgpr_32 = COPY %13
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BUFFER_STORE_DWORD_OFFSET_exact killed %14, %4, %5, 4, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# Check exit of WQM is still inserted correctly when SCC is live until block end.
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# Critially this tests that compilation does not fail.
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#CHECK-LABEL: name: scc_always_live
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#CHECK: %8:vreg_128 = IMAGE_SAMPLE_V4_V2 %7
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#CHECK-NEXT: S_CMP_EQ_U32 %2, 0, implicit-def $scc
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#CHECK-NEXT: undef %9.sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64
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#CHECK-NEXT: %9.sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32
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#CHECK-NEXT: %14:sreg_32_xm0 = COPY $scc
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#CHECK-NEXT: $exec = S_AND_B64 $exec, %13, implicit-def $scc
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#CHECK-NEXT: $scc = COPY %14
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#CHECK-NEXT: %10:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64
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#CHECK-NEXT: %11:vreg_128 = IMAGE_SAMPLE_V4_V2
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#CHECK-NEXT: S_CBRANCH_SCC0 %bb.2
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name: scc_always_live
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr1, $sgpr2, $vgpr1, $vgpr2
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$m0 = COPY $sgpr1
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%0:vgpr_32 = COPY $vgpr1
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%1:vgpr_32 = COPY $vgpr2
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%8:sgpr_32 = COPY $sgpr2
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%100:sgpr_256 = IMPLICIT_DEF
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%101:sgpr_128 = IMPLICIT_DEF
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%2:vgpr_32 = V_INTERP_P1_F32 %0:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec
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%3:vgpr_32 = V_INTERP_P1_F32 %1:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec
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undef %7.sub0:vreg_64 = COPY %2:vgpr_32
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%7.sub1:vreg_64 = COPY %3:vgpr_32
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%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %7:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
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S_CMP_EQ_U32 %8:sgpr_32, 0, implicit-def $scc
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undef %5.sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64 0, %4.sub0:vreg_128, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec
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%5.sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32 %2, %3, implicit $mode, implicit $exec
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%6:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64 0, %2:vgpr_32, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec
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%9:vreg_128 = IMAGE_SAMPLE_V4_V2 %5:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
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S_CBRANCH_SCC0 %bb.2, implicit $scc
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bb.1:
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%10:sreg_32 = S_MOV_B32 0
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BUFFER_STORE_DWORD_OFFSET_exact %6:vgpr_32, %101:sgpr_128, %10:sreg_32, 4, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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bb.2:
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$vgpr0 = COPY %4.sub0:vreg_128
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$vgpr1 = COPY %4.sub1:vreg_128
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$vgpr2 = COPY %9.sub0:vreg_128
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$vgpr3 = COPY %9.sub1:vreg_128
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SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3
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...
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---
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# Check that unnecessary instruction do not get marked for WWM
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#
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#CHECK-NOT: ENTER_STRICT_WWM
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#CHECK: BUFFER_LOAD_DWORDX2
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#CHECK-NOT: ENTER_STRICT_WWM
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#CHECK: V_SET_INACTIVE_B32
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#CHECK: V_SET_INACTIVE_B32
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#CHECK: ENTER_STRICT_WWM
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#CHECK: V_MAX
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name: test_wwm_set_inactive_propagation
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
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%0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:vgpr_32 = COPY $vgpr0
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%2:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN %1:vgpr_32, %0:sgpr_128, 0, 0, 0, 0, 0, implicit $exec
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%2.sub0:vreg_64 = V_SET_INACTIVE_B32 %2.sub0:vreg_64, 0, implicit $exec, implicit-def $scc
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%2.sub1:vreg_64 = V_SET_INACTIVE_B32 %2.sub1:vreg_64, 0, implicit $exec, implicit-def $scc
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%3:vreg_64 = nnan nsz arcp contract reassoc nofpexcept V_MAX_F64_e64 0, %2:vreg_64, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = STRICT_WWM %3.sub0:vreg_64, implicit $exec
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$vgpr1 = STRICT_WWM %3.sub1:vreg_64, implicit $exec
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SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
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...
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---
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# Check that WQM marking occurs correctly through phi nodes in live range graph.
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# If not then initial V_MOV will not be in WQM.
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#
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#CHECK-LABEL: name: test_wqm_lr_phi
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#CHECK: COPY $exec
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#CHECK-NEXT: S_WQM
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#CHECK-NEXT: V_MOV_B32_e32 -10
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#CHECK-NEXT: V_MOV_B32_e32 0
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name: test_wqm_lr_phi
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tracksRegLiveness: true
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body: |
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bb.0:
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undef %0.sub0:vreg_64 = V_MOV_B32_e32 -10, implicit $exec
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%0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%1:sreg_64 = S_GETPC_B64
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%2:sgpr_256 = S_LOAD_DWORDX8_IMM %1:sreg_64, 32, 0
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bb.1:
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$vcc = V_CMP_LT_U32_e64 4, 4, implicit $exec
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S_CBRANCH_VCCNZ %bb.3, implicit $vcc
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S_BRANCH %bb.2
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bb.2:
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%0.sub0:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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%0.sub1:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec
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S_BRANCH %bb.4
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bb.4:
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%3:sgpr_128 = IMPLICIT_DEF
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%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %2:sgpr_256, %3:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
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$vgpr0 = COPY %4.sub0:vreg_128
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$vgpr1 = COPY %4.sub1:vreg_128
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SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
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...
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---
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#CHECK-LABEL: name: no_wqm_in_cs
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#CHECK-NOT: S_WQM
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name: no_wqm_in_cs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr1, $vgpr2
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undef %0.sub0:vreg_64 = COPY $vgpr1
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%0.sub1:vreg_64 = COPY $vgpr2
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%100:sgpr_256 = IMPLICIT_DEF
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%101:sgpr_128 = IMPLICIT_DEF
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%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
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...
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---
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#CHECK-LABEL: name: no_wqm_in_es
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#CHECK-NOT: S_WQM
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name: no_wqm_in_es
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr1, $vgpr2
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undef %0.sub0:vreg_64 = COPY $vgpr1
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%0.sub1:vreg_64 = COPY $vgpr2
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%100:sgpr_256 = IMPLICIT_DEF
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%101:sgpr_128 = IMPLICIT_DEF
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%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
|
|
...
|
|
|
|
---
|
|
#CHECK-LABEL: name: no_wqm_in_gs
|
|
#CHECK-NOT: S_WQM
|
|
name: no_wqm_in_gs
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr1, $vgpr2
|
|
|
|
undef %0.sub0:vreg_64 = COPY $vgpr1
|
|
%0.sub1:vreg_64 = COPY $vgpr2
|
|
%100:sgpr_256 = IMPLICIT_DEF
|
|
%101:sgpr_128 = IMPLICIT_DEF
|
|
|
|
%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
|
|
...
|
|
|
|
---
|
|
#CHECK-LABEL: name: no_wqm_in_hs
|
|
#CHECK-NOT: S_WQM
|
|
name: no_wqm_in_hs
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr1, $vgpr2
|
|
|
|
undef %0.sub0:vreg_64 = COPY $vgpr1
|
|
%0.sub1:vreg_64 = COPY $vgpr2
|
|
%100:sgpr_256 = IMPLICIT_DEF
|
|
%101:sgpr_128 = IMPLICIT_DEF
|
|
|
|
%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
|
|
...
|
|
|
|
---
|
|
#CHECK-LABEL: name: no_wqm_in_ls
|
|
#CHECK-NOT: S_WQM
|
|
name: no_wqm_in_ls
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr1, $vgpr2
|
|
|
|
undef %0.sub0:vreg_64 = COPY $vgpr1
|
|
%0.sub1:vreg_64 = COPY $vgpr2
|
|
%100:sgpr_256 = IMPLICIT_DEF
|
|
%101:sgpr_128 = IMPLICIT_DEF
|
|
|
|
%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
|
|
...
|
|
|
|
---
|
|
#CHECK-LABEL: name: no_wqm_in_vs
|
|
#CHECK-NOT: S_WQM
|
|
name: no_wqm_in_vs
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr1, $vgpr2
|
|
|
|
undef %0.sub0:vreg_64 = COPY $vgpr1
|
|
%0.sub1:vreg_64 = COPY $vgpr2
|
|
%100:sgpr_256 = IMPLICIT_DEF
|
|
%101:sgpr_128 = IMPLICIT_DEF
|
|
|
|
%4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
|
|
...
|