llvm-project/llvm/test/CodeGen/MIR/AMDGPU
Jon Chesterfield 3a20597776 [amdgpu] Implement lds kernel id intrinsic
Implement an intrinsic for use lowering LDS variables to different
addresses from different kernels. This will allow kernels that cannot
reach an LDS variable to avoid wasting space for it.

There are a number of implicit arguments accessed by intrinsic already
so this implementation closely follows the existing handling. It is slightly
novel in that this SGPR is written by the kernel prologue.

It is necessary in the general case to put variables at different addresses
such that they can be compactly allocated and thus necessary for an
indirect function call to have some means of determining where a
given variable was allocated. Claiming an arbitrary SGPR into which
an integer can be written by the kernel, in this implementation based
on metadata associated with that kernel, which is then passed on to
indirect call sites is sufficient to determine the variable address.

The intent is to emit a __const array of LDS addresses and index into it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D125060
2022-07-19 17:46:19 +01:00
..
custom-pseudo-source-values.ll
dead-flag-on-use-operand-parse-error.mir MIRParser: Fix asserting with invalid flags on machine operands 2022-04-05 21:46:26 -04:00
empty-custom-regmask.mir MIR: Fix parse error on empty CustomRegMask 2022-06-27 08:50:35 -04:00
expected-target-index-name.mir
extra-imm-operand.mir [MIR] Provide location of extra instruction operand when diagnosing it. 2022-05-20 05:56:25 +01:00
extra-reg-operand.mir [MIR] Provide location of extra instruction operand when diagnosing it. 2022-05-20 05:56:25 +01:00
intrinsics.mir
invalid-frame-index-invalid-fixed-stack.mir
invalid-frame-index-invalid-stack.mir
invalid-frame-index-no-stack.mir
invalid-frame-index.mir
invalid-frame-index2.mir
invalid-target-index-operand.mir
killed-flag-on-def-parse-error.mir MIRParser: Fix asserting with invalid flags on machine operands 2022-04-05 21:46:26 -04:00
lit.local.cfg
llc-target-cpu-attr-from-cmdline-ir.mir
llc-target-cpu-attr-from-cmdline.mir
load-store-opt-dlc.mir
machine-function-info-after-pei.ll AMDGPU: Serialize VGPRForAGPRCopy 2022-04-19 22:14:52 -04:00
machine-function-info-dynlds-align-invalid-case.mir
machine-function-info-no-ir.mir [amdgpu] Implement lds kernel id intrinsic 2022-07-19 17:46:19 +01:00
machine-function-info-register-parse-error1.mir
machine-function-info-register-parse-error2.mir
machine-function-info.ll [amdgpu] Implement lds kernel id intrinsic 2022-07-19 17:46:19 +01:00
machine-metadata-error.mir
machine-metadata.mir [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range 2022-03-09 12:18:02 +05:30
mfi-frame-offset-reg-class.mir
mfi-parse-error-frame-offset-reg.mir
mfi-parse-error-scratch-rsrc-reg.mir
mfi-parse-error-stack-ptr-offset-reg.mir
mfi-scratch-rsrc-reg-reg-class.mir
mfi-stack-ptr-offset-reg-class.mir
mir-canon-multi.mir
mircanon-memoperands.mir
parse-order-reserved-regs.mir
stack-id-assert.mir [AMDGPU][NFC] Refactor AMDGPUCallingConv.td 2022-06-01 16:24:09 +00:00
stack-id.mir
subreg-def-is-not-ssa.mir
syncscopes.mir
target-flags.mir
target-index-operands.mir
target-memoperands.mir
vgpr-for-agpr-copy-invalid-reg.mir AMDGPU: Serialize VGPRForAGPRCopy 2022-04-19 22:14:52 -04:00
wwm-reserved-regs-invalid-reg.mir AMDGPU: Serialize WWM registers 2022-04-19 21:44:43 -04:00
wwm-reserved-regs-not-a-reg.mir AMDGPU: Serialize WWM registers 2022-04-19 21:44:43 -04:00
wwm-reserved-regs.mir AMDGPU: Serialize WWM registers 2022-04-19 21:44:43 -04:00