296 lines
8.5 KiB
LLVM
296 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV32
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; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV64
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define iXLen2 @test_udiv_3(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_3:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 3
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_3:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 3
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 3
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_5(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_5:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 5
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_5:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 5
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 5
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_7(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_7:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 7
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_7:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 7
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 7
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_9(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_9:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 9
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_9:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 9
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 9
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_15(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_15:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 15
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_15:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 15
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 15
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_17(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_17:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 17
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_17:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 17
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 17
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_255(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_255:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 255
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_255:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 255
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 255
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_257(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_257:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 257
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_257:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 257
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 257
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_65535(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_65535:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: lui a2, 16
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; RV32-NEXT: addi a2, a2, -1
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_65535:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: lui a2, 16
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; RV64-NEXT: addiw a2, a2, -1
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 65535
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_65537(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_65537:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: lui a2, 16
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; RV32-NEXT: addi a2, a2, 1
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_65537:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: lui a2, 16
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; RV64-NEXT: addiw a2, a2, 1
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 65537
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ret iXLen2 %a
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}
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define iXLen2 @test_udiv_12(iXLen2 %x) nounwind {
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; RV32-LABEL: test_udiv_12:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 12
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __udivdi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_udiv_12:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 12
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __udivti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = udiv iXLen2 %x, 12
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ret iXLen2 %a
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}
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