ab0c5cea0b
This adjusts all the MVE and CDE intrinsics now that v2i1 is a legal type, to use a <2 x i1> as opposed to emulating the predicate with a <4 x i1>. The v4i1 workarounds have been removed leaving the natural v2i1 types, notably in vctp64 which now generates a v2i1 type. AutoUpgrade code has been added to upgrade old IR, which needs to convert the old v4i1 to a v2i1 be converting it back and forth to an integer with arm.mve.v2i and arm.mve.i2v intrinsics. These should be optimized away in the final assembly. Differential Revision: https://reviews.llvm.org/D114455 |
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| .. | ||
| absneg-predicated.ll | ||
| bitwise-imm.ll | ||
| dup.ll | ||
| idup.ll | ||
| load-store.ll | ||
| longshift-const.ll | ||
| longshift-demand.ll | ||
| predicates.ll | ||
| scalar-shifts.ll | ||
| scatter-gather.ll | ||
| ternary.ll | ||
| v2i1-upgrade.ll | ||
| vabavq.ll | ||
| vabdq.ll | ||
| vadc-multiple.ll | ||
| vadc.ll | ||
| vaddq.ll | ||
| vaddv.ll | ||
| vandq.ll | ||
| vbicq.ll | ||
| vbrsrq.ll | ||
| vcaddq.ll | ||
| vcls.ll | ||
| vclzcls-predicated.ll | ||
| vcmlaq.ll | ||
| vcmulq.ll | ||
| vcvt-fp-int.ll | ||
| vcvt.ll | ||
| vcvt_anpm.ll | ||
| vector-shift-imm-dyadic.ll | ||
| vector-shift-imm.ll | ||
| vector-shift-var.ll | ||
| veorq.ll | ||
| vhaddq.ll | ||
| vhsubq.ll | ||
| vld24.ll | ||
| vldr.ll | ||
| vmaxaq.ll | ||
| vmaxnmaq.ll | ||
| vmaxnmq.ll | ||
| vmaxq.ll | ||
| vminaq.ll | ||
| vminnmaq.ll | ||
| vminnmq.ll | ||
| vminq.ll | ||
| vminvq.ll | ||
| vmldav.ll | ||
| vmlldav.ll | ||
| vmovl.ll | ||
| vmovn.ll | ||
| vmulhq.ll | ||
| vmullbq.ll | ||
| vmulltq.ll | ||
| vmulq.ll | ||
| vornq.ll | ||
| vorrq.ll | ||
| vqaddq.ll | ||
| vqdmlad.ll | ||
| vqdmulhq.ll | ||
| vqdmull.ll | ||
| vqmovn.ll | ||
| vqrdmulhq.ll | ||
| vqsubq.ll | ||
| vrev.ll | ||
| vrhaddq.ll | ||
| vrint-predicated.ll | ||
| vrintn.ll | ||
| vrmulhq.ll | ||
| vshlc.ll | ||
| vsubq.ll | ||