72 lines
3.7 KiB
LLVM
72 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
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declare <256 x float> @llvm.vp.fma.v256f32(<256 x float>, <256 x float>, <256 x float>, <256 x i1>, i32)
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define fastcc <256 x float> @test_vp_fma_v256f32_vvv_merge(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {
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; CHECK-LABEL: test_vp_fma_v256f32_vvv_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmad.s %v3, %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v3
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; CHECK-NEXT: b.l.t (, %s10)
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%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)
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%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
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ret <256 x float> %r0
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}
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define fastcc <256 x float> @test_vp_fma_v256f32_rvv_merge(float %s0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {
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; CHECK-LABEL: test_vp_fma_v256f32_rvv_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmad.s %v2, %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x float> undef, float %s0, i32 0
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%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
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%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)
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%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
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ret <256 x float> %r0
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}
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define fastcc <256 x float> @test_vp_fma_v256f32_vrv_merge(<256 x float> %i0, float %s1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {
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; CHECK-LABEL: test_vp_fma_v256f32_vrv_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmad.s %v2, %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x float> undef, float %s1, i32 0
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%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
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%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)
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%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
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ret <256 x float> %r0
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}
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define fastcc <256 x float> @test_vp_fma_v256f32_vvr_merge(<256 x float> %i0, <256 x float> %i1, float %s2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {
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; CHECK-LABEL: test_vp_fma_v256f32_vvr_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmad.s %v2, %s0, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%zins = insertelement <256 x float> undef, float %s2, i32 0
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%i2 = shufflevector <256 x float> %zins, <256 x float> undef, <256 x i32> zeroinitializer
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%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)
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%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
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ret <256 x float> %r0
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}
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