llvm-project/llvm/test/MC/Disassembler
Dmitry Preobrazhensky 4e68834add [AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes
Differential Revision: https://reviews.llvm.org/D131588
2022-08-11 17:12:13 +03:00
..
AArch64 [llvm-objdump,ARM] Fix a lot more tests. 2022-07-26 10:22:02 +01:00
AMDGPU [AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes 2022-08-11 17:12:13 +03:00
ARC [ARC] Add ADC (addition with carry) and SBC (subtraction with carry) instructions 2021-08-25 07:46:15 -07:00
ARM [ARM] Implement PAC return address signing mechanism for PACBTI-M 2021-12-07 10:15:19 +00:00
Hexagon
Lanai
M68k [M68k] Add MC support for link/unlk 2022-08-08 11:00:11 +08:00
MSP430
Mips
PowerPC [PowerPC] Set the special DSCR with a compiler option. 2022-03-31 14:06:30 -05:00
RISCV [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
Sparc
SystemZ Support z16 processor name 2022-04-21 19:58:22 +02:00
WebAssembly
X86 [X86] Add RDPRU instruction 2022-07-06 07:17:47 -07:00
XCore