llvm-project/llvm/test/tools/llvm-mca/X86/Haswell
Craig Topper 56d6ccd4cb [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs
Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.

For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.

The by immediate instructions need 7 or 8 uops and have higher latency.

It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.

Noticed while checking out PR53648. So mostly I cared about the by 1
instructions.

Reviewed By: RKSimon, pengfei

Differential Revision: https://reviews.llvm.org/D119217
2022-02-08 09:20:20 -08:00
..
adcx-adox-read-advance.s
cmpxchg16b.s
independent-load-stores.s
mulx-hi-read-advance.s
mulx-lo-reg-use.s
mulx-read-advance.s
mulx-same-regs.s
reserved-resources.s
resources-avx1.s
resources-avx2.s
resources-bmi1.s
resources-bmi2.s
resources-cmov.s
resources-cmpxchg.s
resources-f16c.s
resources-fma.s
resources-fsgsbase.s
resources-lea.s
resources-lzcnt.s
resources-mmx.s
resources-movbe.s
resources-pclmul.s
resources-popcnt.s
resources-rdrand.s
resources-sse1.s
resources-sse2.s
resources-sse3.s
resources-sse41.s
resources-sse42.s
resources-ssse3.s
resources-x86_32.s
resources-x86_64.s [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs 2022-02-08 09:20:20 -08:00
resources-x87.s
stmxcsr-ldmxcsr.s
zero-idioms.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00