llvm-project/llvm/test/tools/llvm-objdump/ELF
Simon Tatham 72017e9b16 [llvm-objdump,ARM] Fix big-endian AArch32 disassembly.
The ABI for big-endian AArch32, as specified by AAELF32, is above-
averagely complicated. Relocatable object files are expected to store
instruction encodings in byte order matching the ELF file's endianness
(so, big-endian for a BE ELF file). But executable images can
//either// do that //or// store instructions little-endian regardless
of data and ELF endianness (to support BE32 and BE8 platforms
respectively). They signal the latter by setting the EF_ARM_BE8 flag
in the ELF header.

(In the case of the Thumb instruction set, this all means that each
16-bit halfword of a Thumb instruction is stored in one or other
endianness. The two halfwords of a 32-bit Thumb instruction must
appear in the same order no matter what, because the first halfword is
the one that must avoid overlapping the encoding of any 16-bit Thumb
instruction.)

llvm-objdump was unconditionally expecting Arm instructions to be
stored little-endian. So it would correctly disassemble a BE8 image,
but if you gave it a BE32 image or a BE object file, it would retrieve
every instruction in byte-swapped form and disassemble it to
nonsense. (Even an object file output by LLVM itself, because
ARMMCCodeEmitter outputs instructions big-endian in big-endian mode,
which is correct for writing an object file.)

This patch allows llvm-objdump to correctly disassemble all three of
those classes of Arm ELF file. It does it by introducing a new
SubtargetFeature for big-endian instructions, setting it from the ELF
image type and flags during llvm-objdump setup, and teaching both
ARMDisassembler and llvm-objdump itself to pay attention to it when
retrieving instruction data from a section being disassembled.

Differential Revision: https://reviews.llvm.org/D130902
2022-08-08 10:49:51 +01:00
..
AArch64 [llvm-objdump,ARM] Make dumpARMELFData line up with instructions. 2022-07-26 09:35:31 +01:00
AMDGPU [AMDGPU] Add GFX11 llvm-objdump tests 2022-06-14 11:39:50 +01:00
ARM [llvm-objdump,ARM] Fix big-endian AArch32 disassembly. 2022-08-08 10:49:51 +01:00
Hexagon
Inputs
Lanai
Mips
PowerPC [llvm-objdump] Default to --mcpu=future for PPC64 2022-06-30 11:30:35 -07:00
RISCV
call-absolute-symbol.test
dynamic-malformed.test [llvm-objdump] --private-headers: change errors to warnings for dynamic section dumping 2022-03-28 01:00:43 -07:00
dynamic-relocs.test [llvm-objdump] -r: print non-SHF_ALLOC relocations for non-ET_REL files 2022-07-01 09:08:42 -07:00
dynamic-section-machine-specific.test [MIPS] Recognize DT_MIPS_XHASH dynamic table tag 2022-02-23 16:03:14 +03:00
dynamic-section.test
dynsym-version.test
file-headers.test
invalid-phdr.test [llvm-objdump] --private-headers: change errors to warnings for dynamic section dumping 2022-03-28 01:00:43 -07:00
private-headers.test [llvm-objdump][test] dos2unix some files 2022-03-28 00:58:14 -07:00
proc-specific-section.test
program-headers.test [llvm-objdump] --private-headers: change errors to warnings for dynamic section dumping 2022-03-28 01:00:43 -07:00
pt-gnu-property.test
relocations-in-nonreloc.test [llvm-objdump] -r: print non-SHF_ALLOC relocations for non-ET_REL files 2022-07-01 09:08:42 -07:00
relocations.test
symbol-table.test
symbol-visibility.test
verdef.test
verneed.test