606 lines
25 KiB
TableGen
606 lines
25 KiB
TableGen
//== LoongArchInstrInfo.td - Target Description for LoongArch -*- tablegen -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the LoongArch instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LoongArch specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// TODO: Add LoongArch specific DAG Nodes
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// Target-dependent nodes.
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def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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class ImmAsmOperand<string prefix, int width, string suffix>
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: AsmOperandClass {
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let Name = prefix # "Imm" # width # suffix;
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let DiagnosticType = !strconcat("Invalid", Name);
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let RenderMethod = "addImmOperands";
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}
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class SImmAsmOperand<int width, string suffix = "">
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: ImmAsmOperand<"S", width, suffix> {
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}
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class UImmAsmOperand<int width, string suffix = "">
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: ImmAsmOperand<"U", width, suffix> {
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}
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def uimm2 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<2>;
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}
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def uimm2_plus1 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<2, "plus1">;
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let EncoderMethod = "getImmOpValueSub1";
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let DecoderMethod = "decodeUImmOperand<2, 1>";
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}
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def uimm3 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<3>;
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}
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def uimm5 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<5>;
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}
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def uimm6 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<6>;
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}
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def uimm8 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<8>;
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}
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def uimm12 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<12>;
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}
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def uimm14 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<14>;
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}
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def uimm15 : Operand<GRLenVT> {
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let ParserMatchClass = UImmAsmOperand<15>;
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}
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def simm12 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isInt<12>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<12>;
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let DecoderMethod = "decodeSImmOperand<12>";
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}
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def simm14_lsl2 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<14, "lsl2">;
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let EncoderMethod = "getImmOpValueAsr2";
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let DecoderMethod = "decodeSImmOperand<14, 2>";
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}
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def simm16 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<16>;
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let DecoderMethod = "decodeSImmOperand<16>";
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}
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def simm16_lsl2 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<16, "lsl2">;
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let EncoderMethod = "getImmOpValueAsr2";
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let DecoderMethod = "decodeSImmOperand<16, 2>";
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}
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def simm20 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<20>;
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let DecoderMethod = "decodeSImmOperand<20>";
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}
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def simm21_lsl2 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<21, "lsl2">;
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let EncoderMethod = "getImmOpValueAsr2";
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let DecoderMethod = "decodeSImmOperand<21, 2>";
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}
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def simm26_lsl2 : Operand<GRLenVT> {
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let ParserMatchClass = SImmAsmOperand<26, "lsl2">;
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let EncoderMethod = "getImmOpValueAsr2";
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let DecoderMethod = "decodeSImmOperand<26, 2>";
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}
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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include "LoongArchInstrFormats.td"
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include "LoongArchFloatInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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class ALU_3R<bits<17> op, string opstr>
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: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
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class ALU_2R<bits<22> op, string opstr>
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: Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
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class ALU_3RI2<bits<15> op, string opstr, Operand ImmOpnd>
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: Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2), opstr,
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"$rd, $rj, $rk, $imm2">;
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class ALU_3RI3<bits<14> op, string opstr, Operand ImmOpnd>
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: Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3), opstr,
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"$rd, $rj, $rk, $imm3">;
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class ALU_2RI5<bits<17> op, string opstr, Operand ImmOpnd>
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: Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5), opstr,
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"$rd, $rj, $imm5">;
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class ALU_2RI6<bits<16> op, string opstr, Operand ImmOpnd>
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: Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6), opstr,
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"$rd, $rj, $imm6">;
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class ALU_2RI12<bits<10> op, string opstr, Operand ImmOpnd>
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: Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12), opstr,
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"$rd, $rj, $imm12">;
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class ALU_2RI16<bits<6> op, string opstr, Operand ImmOpnd>
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: Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16), opstr,
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"$rd, $rj, $imm16">;
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class ALU_1RI20<bits<7> op, string opstr, Operand ImmOpnd>
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: Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), opstr, "$rd, $imm20">;
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class MISC_I15<bits<17> op, string opstr>
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: FmtI15<op, (outs), (ins uimm15:$imm15), opstr, "$imm15">;
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class RDTIME_2R<bits<22> op, string opstr>
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: Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins), opstr, "$rd, $rj">;
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class BrCC_2RI16<bits<6> op, string opstr>
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: Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2:$imm16), opstr,
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"$rj, $rd, $imm16"> {
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let isBranch = 1;
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let isTerminator = 1;
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}
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class BrCCZ_1RI21<bits<6> op, string opstr>
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: Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr,
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"$rj, $imm21"> {
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let isBranch = 1;
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let isTerminator = 1;
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}
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class Br_I26<bits<6> op, string opstr>
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: FmtI26<op, (outs), (ins simm26_lsl2:$imm26), opstr, "$imm26"> {
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let isBranch = 1;
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let isTerminator = 1;
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}
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let mayLoad = 1 in {
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class LOAD_3R<bits<17> op, string opstr>
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: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
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class LOAD_2RI12<bits<10> op, string opstr>
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: Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12:$imm12), opstr,
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"$rd, $rj, $imm12">;
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class LOAD_2RI14<bits<8> op, string opstr>
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: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
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"$rd, $rj, $imm14">;
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} // mayLoad = 1
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let mayStore = 1 in {
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class STORE_3R<bits<17> op, string opstr>
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: Fmt3R<op, (outs), (ins GPR:$rd, GPR:$rj, GPR:$rk), opstr,
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"$rd, $rj, $rk">;
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class STORE_2RI12<bits<10> op, string opstr>
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: Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12:$imm12), opstr,
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"$rd, $rj, $imm12">;
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class STORE_2RI14<bits<8> op, string opstr>
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: Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14), opstr,
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"$rd, $rj, $imm14">;
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} // mayStore = 1
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let mayLoad = 1, mayStore = 1 in
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class AM_3R<bits<17> op, string opstr>
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: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPR:$rj), opstr, "$rd, $rk, $rj">;
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let mayLoad = 1 in
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class LLBase<bits<8> op, string opstr>
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: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
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"$rd, $rj, $imm14">;
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let mayStore = 1, Constraints = "$rd = $dst" in
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class SCBase<bits<8> op, string opstr>
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: Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
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opstr, "$rd, $rj, $imm14">;
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class IOCSRRD<bits<22> op, string opstr>
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: Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
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class IOCSRWR<bits<22> op, string opstr>
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: Fmt2R<op, (outs), (ins GPR:$rd, GPR:$rj), opstr, "$rd, $rj">;
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//===----------------------------------------------------------------------===//
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// Basic Integer Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic Operation Instructions
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def ADD_W : ALU_3R<0b00000000000100000, "add.w">;
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def SUB_W : ALU_3R<0b00000000000100010, "sub.w">;
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def ADDI_W : ALU_2RI12<0b0000001010, "addi.w", simm12>;
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def ALSL_W : ALU_3RI2<0b000000000000010, "alsl.w", uimm2_plus1>;
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def LU12I_W : ALU_1RI20<0b0001010, "lu12i.w", simm20>;
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def SLT : ALU_3R<0b00000000000100100, "slt">;
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def SLTU : ALU_3R<0b00000000000100101, "sltu">;
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def SLTI : ALU_2RI12<0b0000001000, "slti", simm12>;
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def SLTUI : ALU_2RI12<0b0000001001, "sltui", simm12>;
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def PCADDI : ALU_1RI20<0b0001100, "pcaddi", simm20>;
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def PCADDU12I : ALU_1RI20<0b0001110, "pcaddu12i", simm20>;
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def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20>;
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def AND : ALU_3R<0b00000000000101001, "and">;
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def OR : ALU_3R<0b00000000000101010, "or">;
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def NOR : ALU_3R<0b00000000000101000, "nor">;
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def XOR : ALU_3R<0b00000000000101011, "xor">;
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def ANDN : ALU_3R<0b00000000000101101, "andn">;
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def ORN : ALU_3R<0b00000000000101100, "orn">;
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def ANDI : ALU_2RI12<0b0000001101, "andi", uimm12>;
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def ORI : ALU_2RI12<0b0000001110, "ori", uimm12>;
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def XORI : ALU_2RI12<0b0000001111, "xori", uimm12>;
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def MUL_W : ALU_3R<0b00000000000111000, "mul.w">;
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def MULH_W : ALU_3R<0b00000000000111001, "mulh.w">;
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def MULH_WU : ALU_3R<0b00000000000111010, "mulh.wu">;
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def DIV_W : ALU_3R<0b00000000001000000, "div.w">;
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def MOD_W : ALU_3R<0b00000000001000001, "mod.w">;
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def DIV_WU : ALU_3R<0b00000000001000010, "div.wu">;
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def MOD_WU : ALU_3R<0b00000000001000011, "mod.wu">;
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// Bit-shift Instructions
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def SLL_W : ALU_3R<0b00000000000101110, "sll.w">;
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def SRL_W : ALU_3R<0b00000000000101111, "srl.w">;
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def SRA_W : ALU_3R<0b00000000000110000, "sra.w">;
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def ROTR_W : ALU_3R<0b00000000000110110, "rotr.w">;
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def SLLI_W : ALU_2RI5<0b00000000010000001, "slli.w", uimm5>;
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def SRLI_W : ALU_2RI5<0b00000000010001001, "srli.w", uimm5>;
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def SRAI_W : ALU_2RI5<0b00000000010010001, "srai.w", uimm5>;
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def ROTRI_W : ALU_2RI5<0b00000000010011001, "rotri.w", uimm5>;
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// Bit-manipulation Instructions
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def EXT_W_B : ALU_2R<0b0000000000000000010111, "ext.w.b">;
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def EXT_W_H : ALU_2R<0b0000000000000000010110, "ext.w.h">;
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def CLO_W : ALU_2R<0b0000000000000000000100, "clo.w">;
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def CLZ_W : ALU_2R<0b0000000000000000000101, "clz.w">;
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def CTO_W : ALU_2R<0b0000000000000000000110, "cto.w">;
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def CTZ_W : ALU_2R<0b0000000000000000000111, "ctz.w">;
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def BYTEPICK_W : ALU_3RI2<0b000000000000100, "bytepick.w", uimm2>;
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def REVB_2H : ALU_2R<0b0000000000000000001100, "revb.2h">;
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def BITREV_4B : ALU_2R<0b0000000000000000010010, "bitrev.4b">;
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def BITREV_W : ALU_2R<0b0000000000000000010100, "bitrev.w">;
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let Constraints = "$rd = $dst" in {
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def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst),
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(ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
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"bstrins.w", "$rd, $rj, $msbw, $lsbw">;
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}
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def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd),
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(ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
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"bstrpick.w", "$rd, $rj, $msbw, $lsbw">;
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def MASKEQZ : ALU_3R<0b00000000000100110, "maskeqz">;
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def MASKNEZ : ALU_3R<0b00000000000100111, "masknez">;
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// Branch Instructions
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def BEQ : BrCC_2RI16<0b010110, "beq">;
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def BNE : BrCC_2RI16<0b010111, "bne">;
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def BLT : BrCC_2RI16<0b011000, "blt">;
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def BGE : BrCC_2RI16<0b011001, "bge">;
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def BLTU : BrCC_2RI16<0b011010, "bltu">;
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def BGEU : BrCC_2RI16<0b011011, "bgeu">;
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def BEQZ : BrCCZ_1RI21<0b010000, "beqz">;
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def BNEZ : BrCCZ_1RI21<0b010001, "bnez">;
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def B : Br_I26<0b010100, "b">;
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let isCall = 1 in
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def BL : FmtI26<0b010101, (outs), (ins simm26_lsl2:$imm26), "bl", "$imm26">;
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def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
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(ins GPR:$rj, simm16_lsl2:$imm16), "jirl",
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"$rd, $rj, $imm16">;
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// Common Memory Access Instructions
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def LD_B : LOAD_2RI12<0b0010100000, "ld.b">;
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def LD_H : LOAD_2RI12<0b0010100001, "ld.h">;
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def LD_W : LOAD_2RI12<0b0010100010, "ld.w">;
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def LD_BU : LOAD_2RI12<0b0010101000, "ld.bu">;
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def LD_HU : LOAD_2RI12<0b0010101001, "ld.hu">;
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def ST_B : STORE_2RI12<0b0010100100, "st.b">;
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def ST_H : STORE_2RI12<0b0010100101, "st.h">;
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def ST_W : STORE_2RI12<0b0010100110, "st.w">;
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def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "preld",
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"$imm5, $rj, $imm12">;
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// Atomic Memory Access Instructions
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def LL_W : LLBase<0b00100000, "ll.w">;
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def SC_W : SCBase<0b00100001, "sc.w">;
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// Barrier Instructions
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def DBAR : MISC_I15<0b00111000011100100, "dbar">;
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def IBAR : MISC_I15<0b00111000011100101, "ibar">;
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// Other Miscellaneous Instructions
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def SYSCALL : MISC_I15<0b00000000001010110, "syscall">;
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def BREAK : MISC_I15<0b00000000001010100, "break">;
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def RDTIMEL_W : RDTIME_2R<0b0000000000000000011000, "rdtimel.w">;
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def RDTIMEH_W : RDTIME_2R<0b0000000000000000011001, "rdtimeh.w">;
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def CPUCFG : ALU_2R<0b0000000000000000011011, "cpucfg">;
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/// LA64 instructions
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let Predicates = [IsLA64] in {
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// Arithmetic Operation Instructions for 64-bits
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def ADD_D : ALU_3R<0b00000000000100001, "add.d">;
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def SUB_D : ALU_3R<0b00000000000100011, "sub.d">;
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def ADDI_D : ALU_2RI12<0b0000001011, "addi.d", simm12>;
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def ADDU16I_D : ALU_2RI16<0b000100, "addu16i.d", simm16>;
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def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>;
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def ALSL_D : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>;
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let Constraints = "$rd = $dst" in {
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def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst),
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(ins GPR:$rd, simm20:$imm20), "lu32i.d",
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"$rd, $imm20">;
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}
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def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12>;
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def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>;
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def MUL_D : ALU_3R<0b00000000000111011, "mul.d">;
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def MULH_D : ALU_3R<0b00000000000111100, "mulh.d">;
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def MULH_DU : ALU_3R<0b00000000000111101, "mulh.du">;
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def MULW_D_W : ALU_3R<0b00000000000111110, "mulw.d.w">;
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|
def MULW_D_WU : ALU_3R<0b00000000000111111, "mulw.d.wu">;
|
|
def DIV_D : ALU_3R<0b00000000001000100, "div.d">;
|
|
def MOD_D : ALU_3R<0b00000000001000101, "mod.d">;
|
|
def DIV_DU : ALU_3R<0b00000000001000110, "div.du">;
|
|
def MOD_DU : ALU_3R<0b00000000001000111, "mod.du">;
|
|
|
|
// Bit-shift Instructions for 64-bits
|
|
def SLL_D : ALU_3R<0b00000000000110001, "sll.d">;
|
|
def SRL_D : ALU_3R<0b00000000000110010, "srl.d">;
|
|
def SRA_D : ALU_3R<0b00000000000110011, "sra.d">;
|
|
def ROTR_D : ALU_3R<0b00000000000110111, "rotr.d">;
|
|
def SLLI_D : ALU_2RI6<0b0000000001000001, "slli.d", uimm6>;
|
|
def SRLI_D : ALU_2RI6<0b0000000001000101, "srli.d", uimm6>;
|
|
def SRAI_D : ALU_2RI6<0b0000000001001001, "srai.d", uimm6>;
|
|
def ROTRI_D : ALU_2RI6<0b0000000001001101, "rotri.d", uimm6>;
|
|
|
|
// Bit-manipulation Instructions for 64-bits
|
|
def CLO_D : ALU_2R<0b0000000000000000001000, "clo.d">;
|
|
def CLZ_D : ALU_2R<0b0000000000000000001001, "clz.d">;
|
|
def CTO_D : ALU_2R<0b0000000000000000001010, "cto.d">;
|
|
def CTZ_D : ALU_2R<0b0000000000000000001011, "ctz.d">;
|
|
def BYTEPICK_D : ALU_3RI3<0b00000000000011, "bytepick.d", uimm3>;
|
|
def REVB_4H : ALU_2R<0b0000000000000000001101, "revb.4h">;
|
|
def REVB_2W : ALU_2R<0b0000000000000000001110, "revb.2w">;
|
|
def REVB_D : ALU_2R<0b0000000000000000001111, "revb.d">;
|
|
def REVH_2W : ALU_2R<0b0000000000000000010000, "revh.2w">;
|
|
def REVH_D : ALU_2R<0b0000000000000000010001, "revh.d">;
|
|
def BITREV_8B : ALU_2R<0b0000000000000000010011, "bitrev.8b">;
|
|
def BITREV_D : ALU_2R<0b0000000000000000010101, "bitrev.d">;
|
|
let Constraints = "$rd = $dst" in {
|
|
def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst),
|
|
(ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
|
|
"bstrins.d", "$rd, $rj, $msbd, $lsbd">;
|
|
}
|
|
def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd),
|
|
(ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
|
|
"bstrpick.d", "$rd, $rj, $msbd, $lsbd">;
|
|
|
|
// Common Memory Access Instructions for 64-bits
|
|
def LD_WU : LOAD_2RI12<0b0010101010, "ld.wu">;
|
|
def LD_D : LOAD_2RI12<0b0010100011, "ld.d">;
|
|
def ST_D : STORE_2RI12<0b0010100111, "st.d">;
|
|
def LDX_B : LOAD_3R<0b00111000000000000, "ldx.b">;
|
|
def LDX_H : LOAD_3R<0b00111000000001000, "ldx.h">;
|
|
def LDX_W : LOAD_3R<0b00111000000010000, "ldx.w">;
|
|
def LDX_D : LOAD_3R<0b00111000000011000, "ldx.d">;
|
|
def LDX_BU : LOAD_3R<0b00111000001000000, "ldx.bu">;
|
|
def LDX_HU : LOAD_3R<0b00111000001001000, "ldx.hu">;
|
|
def LDX_WU : LOAD_3R<0b00111000001010000, "ldx.wu">;
|
|
def STX_B : STORE_3R<0b00111000000100000, "stx.b">;
|
|
def STX_H : STORE_3R<0b00111000000101000, "stx.h">;
|
|
def STX_W : STORE_3R<0b00111000000110000, "stx.w">;
|
|
def STX_D : STORE_3R<0b00111000000111000, "stx.d">;
|
|
def LDPTR_W : LOAD_2RI14<0b00100100, "ldptr.w">;
|
|
def LDPTR_D : LOAD_2RI14<0b00100110, "ldptr.d">;
|
|
def STPTR_W : STORE_2RI14<0b00100101, "stptr.w">;
|
|
def STPTR_D : STORE_2RI14<0b00100111, "stptr.d">;
|
|
def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "preldx",
|
|
"$imm5, $rj, $rk">;
|
|
|
|
// Bound Check Memory Access Instructions
|
|
def LDGT_B : LOAD_3R<0b00111000011110000, "ldgt.b">;
|
|
def LDGT_H : LOAD_3R<0b00111000011110001, "ldgt.h">;
|
|
def LDGT_W : LOAD_3R<0b00111000011110010, "ldgt.w">;
|
|
def LDGT_D : LOAD_3R<0b00111000011110011, "ldgt.d">;
|
|
def LDLE_B : LOAD_3R<0b00111000011110100, "ldle.b">;
|
|
def LDLE_H : LOAD_3R<0b00111000011110101, "ldle.h">;
|
|
def LDLE_W : LOAD_3R<0b00111000011110110, "ldle.w">;
|
|
def LDLE_D : LOAD_3R<0b00111000011110111, "ldle.d">;
|
|
def STGT_B : STORE_3R<0b00111000011111000, "stgt.b">;
|
|
def STGT_H : STORE_3R<0b00111000011111001, "stgt.h">;
|
|
def STGT_W : STORE_3R<0b00111000011111010, "stgt.w">;
|
|
def STGT_D : STORE_3R<0b00111000011111011, "stgt.d">;
|
|
def STLE_B : STORE_3R<0b00111000011111100, "stle.b">;
|
|
def STLE_H : STORE_3R<0b00111000011111101, "stle.h">;
|
|
def STLE_W : STORE_3R<0b00111000011111110, "stle.w">;
|
|
def STLE_D : STORE_3R<0b00111000011111111, "stle.d">;
|
|
|
|
// Atomic Memory Access Instructions for 64-bits
|
|
def AMSWAP_W : AM_3R<0b00111000011000000, "amswap.w">;
|
|
def AMSWAP_D : AM_3R<0b00111000011000001, "amswap.d">;
|
|
def AMADD_W : AM_3R<0b00111000011000010, "amadd.w">;
|
|
def AMADD_D : AM_3R<0b00111000011000011, "amadd.d">;
|
|
def AMAND_W : AM_3R<0b00111000011000100, "amand.w">;
|
|
def AMAND_D : AM_3R<0b00111000011000101, "amand.d">;
|
|
def AMOR_W : AM_3R<0b00111000011000110, "amor.w">;
|
|
def AMOR_D : AM_3R<0b00111000011000111, "amor.d">;
|
|
def AMXOR_W : AM_3R<0b00111000011001000, "amxor.w">;
|
|
def AMXOR_D : AM_3R<0b00111000011001001, "amxor.d">;
|
|
def AMMAX_W : AM_3R<0b00111000011001010, "ammax.w">;
|
|
def AMMAX_D : AM_3R<0b00111000011001011, "ammax.d">;
|
|
def AMMIN_W : AM_3R<0b00111000011001100, "ammin.w">;
|
|
def AMMIN_D : AM_3R<0b00111000011001101, "ammin.d">;
|
|
def AMMAX_WU : AM_3R<0b00111000011001110, "ammax.wu">;
|
|
def AMMAX_DU : AM_3R<0b00111000011001111, "ammax.du">;
|
|
def AMMIN_WU : AM_3R<0b00111000011010000, "ammin.wu">;
|
|
def AMMIN_DU : AM_3R<0b00111000011010001, "ammin.du">;
|
|
def AMSWAP_DB_W : AM_3R<0b00111000011010010, "amswap_db.w">;
|
|
def AMSWAP_DB_D : AM_3R<0b00111000011010011, "amswap_db.d">;
|
|
def AMADD_DB_W : AM_3R<0b00111000011010100, "amadd_db.w">;
|
|
def AMADD_DB_D : AM_3R<0b00111000011010101, "amadd_db.d">;
|
|
def AMAND_DB_W : AM_3R<0b00111000011010110, "amand_db.w">;
|
|
def AMAND_DB_D : AM_3R<0b00111000011010111, "amand_db.d">;
|
|
def AMOR_DB_W : AM_3R<0b00111000011011000, "amor_db.w">;
|
|
def AMOR_DB_D : AM_3R<0b00111000011011001, "amor_db.d">;
|
|
def AMXOR_DB_W : AM_3R<0b00111000011011010, "amxor_db.w">;
|
|
def AMXOR_DB_D : AM_3R<0b00111000011011011, "amxor_db.d">;
|
|
def AMMAX_DB_W : AM_3R<0b00111000011011100, "ammax_db.w">;
|
|
def AMMAX_DB_D : AM_3R<0b00111000011011101, "ammax_db.d">;
|
|
def AMMIN_DB_W : AM_3R<0b00111000011011110, "ammin_db.w">;
|
|
def AMMIN_DB_D : AM_3R<0b00111000011011111, "ammin_db.d">;
|
|
def AMMAX_DB_WU : AM_3R<0b00111000011100000, "ammax_db.wu">;
|
|
def AMMAX_DB_DU : AM_3R<0b00111000011100001, "ammax_db.du">;
|
|
def AMMIN_DB_WU : AM_3R<0b00111000011100010, "ammin_db.wu">;
|
|
def AMMIN_DB_DU : AM_3R<0b00111000011100011, "ammin_db.du">;
|
|
def LL_D : LLBase<0b00100010, "ll.d">;
|
|
def SC_D : SCBase<0b00100011, "sc.d">;
|
|
|
|
// CRC Check Instructions
|
|
def CRC_W_B_W : ALU_3R<0b00000000001001000, "crc.w.b.w">;
|
|
def CRC_W_H_W : ALU_3R<0b00000000001001001, "crc.w.h.w">;
|
|
def CRC_W_W_W : ALU_3R<0b00000000001001010, "crc.w.w.w">;
|
|
def CRC_W_D_W : ALU_3R<0b00000000001001011, "crc.w.d.w">;
|
|
def CRCC_W_B_W : ALU_3R<0b00000000001001100, "crcc.w.b.w">;
|
|
def CRCC_W_H_W : ALU_3R<0b00000000001001101, "crcc.w.h.w">;
|
|
def CRCC_W_W_W : ALU_3R<0b00000000001001110, "crcc.w.w.w">;
|
|
def CRCC_W_D_W : ALU_3R<0b00000000001001111, "crcc.w.d.w">;
|
|
|
|
// Other Miscellaneous Instructions for 64-bits
|
|
def ASRTLE_D : FmtASRT<0b00000000000000010, (outs), (ins GPR:$rj, GPR:$rk),
|
|
"asrtle.d", "$rj, $rk">;
|
|
def ASRTGT_D : FmtASRT<0b00000000000000011, (outs), (ins GPR:$rj, GPR:$rk),
|
|
"asrtgt.d", "$rj, $rk">;
|
|
def RDTIME_D : RDTIME_2R<0b0000000000000000011010, "rdtime.d">;
|
|
} // Predicates = [IsLA64]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo-instructions and codegen patterns
|
|
//
|
|
// Naming convention: For 'generic' pattern classes, we use the naming
|
|
// convention PatTy1Ty2.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Generic pattern classes
|
|
|
|
class PatGprGpr<SDPatternOperator OpNode, LAInst Inst>
|
|
: Pat<(OpNode GPR:$rj, GPR:$rk), (Inst GPR:$rj, GPR:$rk)>;
|
|
class PatGprGpr_32<SDPatternOperator OpNode, LAInst Inst>
|
|
: Pat<(sext_inreg (OpNode GPR:$rj, GPR:$rk), i32), (Inst GPR:$rj, GPR:$rk)>;
|
|
|
|
class PatGprImm<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
|
|
: Pat<(OpNode GPR:$rj, ImmOpnd:$imm),
|
|
(Inst GPR:$rj, ImmOpnd:$imm)>;
|
|
class PatGprImm_32<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
|
|
: Pat<(sext_inreg (OpNode GPR:$rj, ImmOpnd:$imm), i32),
|
|
(Inst GPR:$rj, ImmOpnd:$imm)>;
|
|
|
|
def : PatGprGpr<and, AND>;
|
|
def : PatGprGpr<or, OR>;
|
|
def : PatGprGpr<xor, XOR>;
|
|
|
|
/// Branches and jumps
|
|
|
|
let isBarrier = 1, isReturn = 1, isTerminator = 1 in
|
|
def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
|
|
PseudoInstExpansion<(JIRL R0, R1, 0)>;
|
|
|
|
/// LA32 patterns
|
|
|
|
let Predicates = [IsLA32] in {
|
|
def : PatGprGpr<add, ADD_W>;
|
|
def : PatGprImm<add, ADDI_W, simm12>;
|
|
} // Predicates = [IsLA32]
|
|
|
|
/// LA64 patterns
|
|
|
|
let Predicates = [IsLA64] in {
|
|
def : Pat<(sext_inreg GPR:$rj, i32), (ADDI_W GPR:$rj, 0)>;
|
|
|
|
def : PatGprGpr<add, ADD_D>;
|
|
def : PatGprGpr_32<add, ADD_W>;
|
|
|
|
def : PatGprImm<add, ADDI_D, simm12>;
|
|
def : PatGprImm_32<add, ADDI_W, simm12>;
|
|
} // Predicates = [IsLA64]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembler Pseudo Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstAlias<"nop", (ANDI R0, R0, 0)>;
|
|
def : InstAlias<"move $dst, $src", (OR GPR:$dst, GPR:$src, R0)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Basic Floating-Point Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "LoongArchFloat32InstrInfo.td"
|
|
include "LoongArchFloat64InstrInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Privilege Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// CSR Access Instructions
|
|
def CSRRD : FmtCSR<0b0000010000000, (outs GPR:$rd), (ins uimm14:$csr_num),
|
|
"csrrd", "$rd, $csr_num">;
|
|
let Constraints = "$rd = $dst" in {
|
|
def CSRWR : FmtCSR<0b0000010000001, (outs GPR:$dst),
|
|
(ins GPR:$rd, uimm14:$csr_num), "csrwr", "$rd, $csr_num">;
|
|
def CSRXCHG : FmtCSRXCHG<0b00000100, (outs GPR:$dst),
|
|
(ins GPR:$rd, GPR:$rj, uimm14:$csr_num),
|
|
"csrxchg", "$rd, $rj, $csr_num">;
|
|
} // Constraints = "$rd = $dst"
|
|
|
|
// IOCSR Access Instructions
|
|
def IOCSRRD_B : IOCSRRD<0b0000011001001000000000, "iocsrrd.b">;
|
|
def IOCSRRD_H : IOCSRRD<0b0000011001001000000001, "iocsrrd.h">;
|
|
def IOCSRRD_W : IOCSRRD<0b0000011001001000000010, "iocsrrd.w">;
|
|
def IOCSRWR_B : IOCSRWR<0b0000011001001000000100, "iocsrwr.b">;
|
|
def IOCSRWR_H : IOCSRWR<0b0000011001001000000101, "iocsrwr.h">;
|
|
def IOCSRWR_W : IOCSRWR<0b0000011001001000000110, "iocsrwr.w">;
|
|
let Predicates = [IsLA64] in {
|
|
def IOCSRRD_D : IOCSRRD<0b0000011001001000000011, "iocsrrd.d">;
|
|
def IOCSRWR_D : IOCSRWR<0b0000011001001000000111, "iocsrwr.d">;
|
|
} // Predicates = [IsLA64]
|
|
|
|
// Cache Maintenance Instructions
|
|
def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12), "cacop",
|
|
"$op, $rj, $imm12">;
|
|
|
|
// TLB Maintenance Instructions
|
|
def TLBSRCH : FmtI32<0b00000110010010000010100000000000, "tlbsrch">;
|
|
def TLBRD : FmtI32<0b00000110010010000010110000000000, "tlbrd">;
|
|
def TLBWR : FmtI32<0b00000110010010000011000000000000, "tlbwr">;
|
|
def TLBFILL : FmtI32<0b00000110010010000011010000000000, "tlbfill">;
|
|
def TLBCLR : FmtI32<0b00000110010010000010000000000000, "tlbclr">;
|
|
def TLBFLUSH : FmtI32<0b00000110010010000010010000000000, "tlbflush">;
|
|
def INVTLB : FmtINVTLB<(outs), (ins GPR:$rk, GPR:$rj, uimm5:$op), "invtlb",
|
|
"$op, $rj, $rk">;
|
|
|
|
// Software Page Walking Instructions
|
|
def LDDIR : Fmt2RI8<0b00000110010000, (outs GPR:$rd),
|
|
(ins GPR:$rj, uimm8:$imm8), "lddir", "$rd, $rj, $imm8">;
|
|
def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "ldpte", "$rj, $seq">;
|
|
|
|
|
|
// Other Miscellaneous Instructions
|
|
def ERTN : FmtI32<0b00000110010010000011100000000000, "ertn">;
|
|
def DBCL : MISC_I15<0b00000000001010101, "dbcl">;
|
|
def IDLE : MISC_I15<0b00000110010010001, "idle">;
|