131 lines
4.7 KiB
C++
131 lines
4.7 KiB
C++
//===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass which lower AMX tile copy instructions. Since
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// there is no tile copy instruction, we need store tile register to stack
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// and load from stack to another tile register. We need extra GR to hold
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// the stride, and we need stack slot to hold the tile data register.
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// We would run this pass after copy propagation, so that we don't miss copy
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// optimization. And we would run this pass before prolog/epilog insertion,
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// so that we can allocate stack slot.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-lower-tile-copy"
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namespace {
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class X86LowerTileCopy : public MachineFunctionPass {
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public:
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static char ID;
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X86LowerTileCopy() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
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};
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} // namespace
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char X86LowerTileCopy::ID = 0;
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INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
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false, false)
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INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
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false, false)
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void X86LowerTileCopy::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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FunctionPass *llvm::createX86LowerTileCopyPass() {
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return new X86LowerTileCopy();
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}
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bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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const X86InstrInfo *TII = ST.getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
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if (!MI.isCopy())
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continue;
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MachineOperand &DstMO = MI.getOperand(0);
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MachineOperand &SrcMO = MI.getOperand(1);
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Register SrcReg = SrcMO.getReg();
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Register DstReg = DstMO.getReg();
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if (!X86::TILERegClass.contains(DstReg, SrcReg))
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continue;
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const TargetRegisterInfo *TRI = ST.getRegisterInfo();
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// Allocate stack slot for tile register
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unsigned Size = TRI->getSpillSize(X86::TILERegClass);
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Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
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int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
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// Allocate stack slot for stride register
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Size = TRI->getSpillSize(X86::GR64RegClass);
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Alignment = TRI->getSpillAlign(X86::GR64RegClass);
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int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
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// TODO: Pick a killed regiter to avoid save/reload. There is problem
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// to get live interval in this stage.
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Register GR64Cand = X86::RAX;
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const DebugLoc &DL = MI.getDebugLoc();
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// mov %rax (%sp)
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BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
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.addReg(GR64Cand);
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// mov 64 %rax
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BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
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// tilestored %tmm, (%sp, %idx)
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unsigned Opc = X86::TILESTORED;
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MachineInstr *NewMI =
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
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.addReg(SrcReg, getKillRegState(SrcMO.isKill()));
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MachineOperand &MO = NewMI->getOperand(2);
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MO.setReg(GR64Cand);
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MO.setIsKill(true);
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// tileloadd (%sp, %idx), %tmm
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Opc = X86::TILELOADD;
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NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
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TileSS);
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// restore %rax
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// mov (%sp) %rax
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
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StrideSS);
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MI.eraseFromParent();
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Changed = true;
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}
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}
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return Changed;
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}
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