360 lines
12 KiB
LLVM
360 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=FLAT %s
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define amdgpu_kernel void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) {
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; SI-LABEL: break_inserted_outside_of_loop:
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; SI: ; %bb.0: ; %main_body
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; SI-NEXT: s_load_dword s2, s[0:1], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_and_b32_e32 v0, s2, v0
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; SI-NEXT: v_and_b32_e32 v0, 1, v0
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: .LBB0_1: ; %ENDIF
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_and_b64 s[4:5], exec, vcc
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; SI-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
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; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; SI-NEXT: s_cbranch_execnz .LBB0_1
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; SI-NEXT: ; %bb.2: ; %ENDLOOP
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; SI-NEXT: s_or_b64 exec, exec, s[2:3]
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; FLAT-LABEL: break_inserted_outside_of_loop:
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; FLAT: ; %bb.0: ; %main_body
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; FLAT-NEXT: s_load_dword s2, s[0:1], 0x2c
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; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; FLAT-NEXT: s_waitcnt lgkmcnt(0)
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; FLAT-NEXT: v_and_b32_e32 v0, s2, v0
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; FLAT-NEXT: v_and_b32_e32 v0, 1, v0
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; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; FLAT-NEXT: s_mov_b64 s[2:3], 0
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; FLAT-NEXT: .LBB0_1: ; %ENDIF
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; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
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; FLAT-NEXT: s_and_b64 s[4:5], exec, vcc
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; FLAT-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
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; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; FLAT-NEXT: s_cbranch_execnz .LBB0_1
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; FLAT-NEXT: ; %bb.2: ; %ENDLOOP
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; FLAT-NEXT: s_or_b64 exec, exec, s[2:3]
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; FLAT-NEXT: s_mov_b32 s3, 0xf000
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; FLAT-NEXT: s_mov_b32 s2, -1
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; FLAT-NEXT: v_mov_b32_e32 v0, 0
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; FLAT-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; FLAT-NEXT: s_endpgm
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main_body:
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%0 = and i32 %a, %tid
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%1 = trunc i32 %0 to i1
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br label %ENDIF
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ENDLOOP:
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store i32 0, i32 addrspace(1)* %out
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ret void
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ENDIF:
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br i1 %1, label %ENDLOOP, label %ENDIF
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}
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define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {
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; SI-LABEL: phi_cond_outside_loop:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
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; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: s_mov_b64 s[4:5], 0
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; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
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; SI-NEXT: s_cbranch_execz .LBB1_2
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; SI-NEXT: ; %bb.1: ; %else
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; SI-NEXT: s_load_dword s0, s[0:1], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_cmp_eq_u32 s0, 0
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; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
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; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec
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; SI-NEXT: .LBB1_2: ; %endif
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; SI-NEXT: s_or_b64 exec, exec, s[6:7]
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; SI-NEXT: .LBB1_3: ; %loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
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; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
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; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; SI-NEXT: s_cbranch_execnz .LBB1_3
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; SI-NEXT: ; %bb.4: ; %exit
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; SI-NEXT: s_endpgm
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;
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; FLAT-LABEL: phi_cond_outside_loop:
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; FLAT: ; %bb.0: ; %entry
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; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; FLAT-NEXT: s_mov_b64 s[2:3], 0
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; FLAT-NEXT: s_mov_b64 s[4:5], 0
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; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc
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; FLAT-NEXT: s_cbranch_execz .LBB1_2
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; FLAT-NEXT: ; %bb.1: ; %else
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; FLAT-NEXT: s_load_dword s0, s[0:1], 0x24
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; FLAT-NEXT: s_waitcnt lgkmcnt(0)
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; FLAT-NEXT: s_cmp_eq_u32 s0, 0
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; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
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; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec
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; FLAT-NEXT: .LBB1_2: ; %endif
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; FLAT-NEXT: s_or_b64 exec, exec, s[6:7]
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; FLAT-NEXT: .LBB1_3: ; %loop
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; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
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; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5]
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; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
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; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; FLAT-NEXT: s_cbranch_execnz .LBB1_3
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; FLAT-NEXT: ; %bb.4: ; %exit
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; FLAT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%0 = icmp eq i32 %tid , 0
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br i1 %0, label %if, label %else
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if:
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br label %endif
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else:
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%1 = icmp eq i32 %b, 0
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br label %endif
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endif:
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%2 = phi i1 [0, %if], [%1, %else]
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br label %loop
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loop:
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br i1 %2, label %exit, label %loop
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exit:
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ret void
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}
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define amdgpu_kernel void @switch_unreachable(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
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; SI-LABEL: switch_unreachable:
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; SI: ; %bb.0: ; %centry
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;
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; FLAT-LABEL: switch_unreachable:
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; FLAT: ; %bb.0: ; %centry
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centry:
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switch i32 %x, label %sw.default [
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i32 0, label %sw.bb
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i32 60, label %sw.bb
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]
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sw.bb:
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unreachable
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sw.default:
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unreachable
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sw.epilog:
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ret void
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}
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declare float @llvm.fabs.f32(float) nounwind readnone
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define amdgpu_kernel void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {
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; SI-LABEL: loop_land_info_assert:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
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; SI-NEXT: s_load_dword s6, s[0:1], 0x0
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; SI-NEXT: s_load_dword s14, s[0:1], 0xc
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; SI-NEXT: v_bfrev_b32_e32 v0, 44
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_cmp_lt_i32 s2, 1
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; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
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; SI-NEXT: s_cmp_lt_i32 s3, 4
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; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
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; SI-NEXT: s_cmp_gt_i32 s3, 3
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; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
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; SI-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
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; SI-NEXT: v_cmp_lt_f32_e64 s[6:7], |s6|, v0
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; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
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; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3]
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; SI-NEXT: s_and_b64 s[4:5], exec, s[6:7]
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: v_mov_b32_e32 v0, 3
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; SI-NEXT: s_branch .LBB3_4
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; SI-NEXT: .LBB3_1: ; %Flow6
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_mov_b64 s[8:9], 0
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; SI-NEXT: .LBB3_2: ; %Flow5
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_mov_b64 s[12:13], 0
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; SI-NEXT: .LBB3_3: ; %Flow
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_and_b64 vcc, exec, s[10:11]
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; SI-NEXT: s_cbranch_vccnz .LBB3_8
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; SI-NEXT: .LBB3_4: ; %while.cond
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_mov_b64 s[12:13], -1
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; SI-NEXT: s_mov_b64 s[8:9], -1
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; SI-NEXT: s_mov_b64 s[10:11], -1
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; SI-NEXT: s_mov_b64 vcc, s[0:1]
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; SI-NEXT: s_cbranch_vccz .LBB3_3
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; SI-NEXT: ; %bb.5: ; %convex.exit
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_mov_b64 s[8:9], -1
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; SI-NEXT: s_mov_b64 s[10:11], -1
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; SI-NEXT: s_mov_b64 vcc, s[2:3]
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; SI-NEXT: s_cbranch_vccz .LBB3_2
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; SI-NEXT: ; %bb.6: ; %if.end
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_mov_b64 s[10:11], -1
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; SI-NEXT: s_mov_b64 vcc, s[4:5]
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; SI-NEXT: s_cbranch_vccz .LBB3_1
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; SI-NEXT: ; %bb.7: ; %if.else
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_mov_b64 s[10:11], 0
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_branch .LBB3_1
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; SI-NEXT: .LBB3_8: ; %loop.exit.guard4
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; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; SI-NEXT: s_and_b64 vcc, exec, s[8:9]
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; SI-NEXT: s_cbranch_vccz .LBB3_4
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; SI-NEXT: ; %bb.9: ; %loop.exit.guard
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; SI-NEXT: s_and_b64 vcc, exec, s[12:13]
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; SI-NEXT: s_cbranch_vccz .LBB3_13
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; SI-NEXT: ; %bb.10: ; %for.cond.preheader
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; SI-NEXT: s_cmpk_lt_i32 s14, 0x3e8
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; SI-NEXT: s_cbranch_scc0 .LBB3_13
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; SI-NEXT: ; %bb.11: ; %for.body
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; SI-NEXT: s_and_b64 vcc, exec, 0
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; SI-NEXT: .LBB3_12: ; %self.loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccz .LBB3_12
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; SI-NEXT: .LBB3_13: ; %DummyReturnBlock
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; SI-NEXT: s_endpgm
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;
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; FLAT-LABEL: loop_land_info_assert:
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; FLAT: ; %bb.0: ; %entry
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; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; FLAT-NEXT: s_load_dword s6, s[0:1], 0x0
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; FLAT-NEXT: s_load_dword s14, s[0:1], 0x30
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; FLAT-NEXT: v_bfrev_b32_e32 v0, 44
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; FLAT-NEXT: s_waitcnt lgkmcnt(0)
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; FLAT-NEXT: s_cmp_lt_i32 s2, 1
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; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
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; FLAT-NEXT: s_cmp_lt_i32 s3, 4
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; FLAT-NEXT: s_cselect_b64 s[4:5], -1, 0
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; FLAT-NEXT: s_cmp_gt_i32 s3, 3
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; FLAT-NEXT: s_cselect_b64 s[2:3], -1, 0
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; FLAT-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
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; FLAT-NEXT: v_cmp_lt_f32_e64 s[6:7], |s6|, v0
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; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5]
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; FLAT-NEXT: s_and_b64 s[2:3], exec, s[2:3]
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; FLAT-NEXT: s_and_b64 s[4:5], exec, s[6:7]
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; FLAT-NEXT: s_mov_b32 s7, 0xf000
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; FLAT-NEXT: s_mov_b32 s6, -1
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; FLAT-NEXT: v_mov_b32_e32 v0, 3
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; FLAT-NEXT: s_branch .LBB3_4
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; FLAT-NEXT: .LBB3_1: ; %Flow6
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_mov_b64 s[8:9], 0
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; FLAT-NEXT: .LBB3_2: ; %Flow5
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_mov_b64 s[12:13], 0
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; FLAT-NEXT: .LBB3_3: ; %Flow
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_and_b64 vcc, exec, s[10:11]
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; FLAT-NEXT: s_cbranch_vccnz .LBB3_8
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; FLAT-NEXT: .LBB3_4: ; %while.cond
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; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
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; FLAT-NEXT: s_mov_b64 s[12:13], -1
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; FLAT-NEXT: s_mov_b64 s[8:9], -1
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; FLAT-NEXT: s_mov_b64 s[10:11], -1
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; FLAT-NEXT: s_mov_b64 vcc, s[0:1]
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; FLAT-NEXT: s_cbranch_vccz .LBB3_3
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; FLAT-NEXT: ; %bb.5: ; %convex.exit
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_mov_b64 s[8:9], -1
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; FLAT-NEXT: s_mov_b64 s[10:11], -1
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; FLAT-NEXT: s_mov_b64 vcc, s[2:3]
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; FLAT-NEXT: s_cbranch_vccz .LBB3_2
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; FLAT-NEXT: ; %bb.6: ; %if.end
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_mov_b64 s[10:11], -1
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; FLAT-NEXT: s_mov_b64 vcc, s[4:5]
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; FLAT-NEXT: s_cbranch_vccz .LBB3_1
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; FLAT-NEXT: ; %bb.7: ; %if.else
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_mov_b64 s[10:11], 0
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; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; FLAT-NEXT: s_waitcnt vmcnt(0)
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; FLAT-NEXT: s_branch .LBB3_1
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; FLAT-NEXT: .LBB3_8: ; %loop.exit.guard4
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; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT-NEXT: s_and_b64 vcc, exec, s[8:9]
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; FLAT-NEXT: s_cbranch_vccz .LBB3_4
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; FLAT-NEXT: ; %bb.9: ; %loop.exit.guard
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; FLAT-NEXT: s_and_b64 vcc, exec, s[12:13]
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; FLAT-NEXT: s_cbranch_vccz .LBB3_13
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; FLAT-NEXT: ; %bb.10: ; %for.cond.preheader
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; FLAT-NEXT: s_cmpk_lt_i32 s14, 0x3e8
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; FLAT-NEXT: s_cbranch_scc0 .LBB3_13
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; FLAT-NEXT: ; %bb.11: ; %for.body
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; FLAT-NEXT: s_and_b64 vcc, exec, 0
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; FLAT-NEXT: .LBB3_12: ; %self.loop
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; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
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; FLAT-NEXT: s_mov_b64 vcc, vcc
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; FLAT-NEXT: s_cbranch_vccz .LBB3_12
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; FLAT-NEXT: .LBB3_13: ; %DummyReturnBlock
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; FLAT-NEXT: s_endpgm
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entry:
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%cmp = icmp sgt i32 %c0, 0
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br label %while.cond.outer
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while.cond.outer:
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%tmp = load float, float addrspace(1)* undef
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br label %while.cond
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while.cond:
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%cmp1 = icmp slt i32 %c1, 4
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br i1 %cmp1, label %convex.exit, label %for.cond
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convex.exit:
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%or = or i1 %cmp, %cmp1
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br i1 %or, label %return, label %if.end
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if.end:
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%tmp3 = call float @llvm.fabs.f32(float %tmp) nounwind readnone
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%cmp2 = fcmp olt float %tmp3, 0x3E80000000000000
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br i1 %cmp2, label %if.else, label %while.cond.outer
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|
|
if.else:
|
|
store volatile i32 3, i32 addrspace(1)* undef, align 4
|
|
br label %while.cond
|
|
|
|
for.cond:
|
|
%cmp3 = icmp slt i32 %c3, 1000
|
|
br i1 %cmp3, label %for.body, label %return
|
|
|
|
for.body:
|
|
br i1 %cmp3, label %self.loop, label %if.end.2
|
|
|
|
if.end.2:
|
|
%or.cond2 = or i1 %cmp3, %arg
|
|
br i1 %or.cond2, label %return, label %for.cond
|
|
|
|
self.loop:
|
|
br label %self.loop
|
|
|
|
return:
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
|
|
|
|
attributes #0 = { nounwind readnone }
|