64 lines
2.1 KiB
LLVM
64 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10BE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9
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define <8 x i16> @test1(i16* %a) {
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; CHECK-P10LE-LABEL: test1:
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; CHECK-P10LE: # %bb.0: # %entry
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; CHECK-P10LE-NEXT: lxvrhx v2, 0, r3
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; CHECK-P10LE-NEXT: blr
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;
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; CHECK-P10BE-LABEL: test1:
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; CHECK-P10BE: # %bb.0: # %entry
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; CHECK-P10BE-NEXT: lxsihzx v2, 0, r3
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; CHECK-P10BE-NEXT: vsplth v2, v2, 3
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; CHECK-P10BE-NEXT: blr
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;
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; CHECK-P9-LABEL: test1:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: lxsihzx v2, 0, r3
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; CHECK-P9-NEXT: vsplth v2, v2, 3
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; CHECK-P9-NEXT: blr
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entry:
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%0 = load i16, i16* %a, align 2
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%vecinit = insertelement <8 x i16> undef, i16 %0, i32 0
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ret <8 x i16> %vecinit
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}
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define <16 x i8> @test2(i8* %a) {
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; CHECK-P10LE-LABEL: test2:
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; CHECK-P10LE: # %bb.0: # %entry
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; CHECK-P10LE-NEXT: lxvrbx v2, 0, r3
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; CHECK-P10LE-NEXT: blr
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;
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; CHECK-P10BE-LABEL: test2:
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; CHECK-P10BE: # %bb.0: # %entry
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; CHECK-P10BE-NEXT: lxsibzx v2, 0, r3
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; CHECK-P10BE-NEXT: vspltb v2, v2, 7
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; CHECK-P10BE-NEXT: blr
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;
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; CHECK-P9-LABEL: test2:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: lxsibzx v2, 0, r3
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; CHECK-P9-NEXT: vspltb v2, v2, 7
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; CHECK-P9-NEXT: blr
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entry:
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%0 = load i8, i8* %a, align 1
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%vecins = insertelement <16 x i8> undef, i8 %0, i32 0
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ret <16 x i8> %vecins
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}
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