83 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			LLVM
		
	
	
	
| ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu  < %s | FileCheck %s
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| ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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| 
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| ; Check the vabsd* instructions that were added in PowerISA V3.0
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| 
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| ; Function Attrs: nounwind readnone
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| declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
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| 
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| ; Function Attrs: nounwind readnone
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| declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
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| 
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| ; Function Attrs: nounwind readnone
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| declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
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| 
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| define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
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| entry:
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|   %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
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|   ret <16 x i8> %res
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| ; CHECK-LABEL: @test_byte
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| ; CHECK: vabsdub 2, 2, 3
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| ; CHECK: blr
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| }
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| 
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| define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
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| entry:
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|   %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
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|   ret <8 x i16> %res
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| ; CHECK-LABEL: @test_half
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| ; CHECK: vabsduh 2, 2, 3
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| ; CHECK: blr
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| }
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| 
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| define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
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| entry:
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|   %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
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|   ret <4 x i32> %res
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| ; CHECK-LABEL: @test_word
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| ; CHECK: vabsduw 2, 2, 3
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| ; CHECK: blr
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| }
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| 
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| define <16 x i8> @test_vabsdub(<16 x i8> %0, <16 x i8> %1) {
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| entry:
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|   %2 = zext <16 x i8> %0 to <16 x i32>
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|   %3 = zext <16 x i8> %1 to <16 x i32>
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|   %4 = sub nsw <16 x i32> %2, %3
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|   %5 = icmp slt <16 x i32> %4, zeroinitializer
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|   %6 = sub nsw <16 x i32> zeroinitializer, %4
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|   %7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %4
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|   %8 = trunc <16 x i32> %7 to <16 x i8>
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|   ret <16 x i8> %8
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| ; CHECK-LABEL: @test_vabsdub
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| ; CHECK: vabsdub 2, 2, 3
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| ; CHECK: blr
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| }
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| 
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| define <8 x i16> @test_vabsduh(<8 x i16> %0, <8 x i16> %1) {
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| entry:
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|   %2 = zext <8 x i16> %0 to <8 x i32>
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|   %3 = zext <8 x i16> %1 to <8 x i32>
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|   %4 = sub nsw <8 x i32> %2, %3
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|   %5 = icmp slt <8 x i32> %4, zeroinitializer
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|   %6 = sub nsw <8 x i32> zeroinitializer, %4
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|   %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4
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|   %8 = trunc <8 x i32> %7 to <8 x i16>
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|   ret <8 x i16> %8
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| ; CHECK-LABEL: @test_vabsduh
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| ; CHECK: vabsduh 2, 2, 3
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| ; CHECK: blr
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| }
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| 
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| define <4 x i32> @test_vabsduw(<4 x i32> %0, <4 x i32> %1) {
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| entry:
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|   %2 = sub nsw <4 x i32> %0, %1
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|   %3 = icmp slt <4 x i32> %2, zeroinitializer
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|   %4 = sub nsw <4 x i32> zeroinitializer, %2
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|   %5 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %2
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|   ret <4 x i32> %5
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| ; CHECK-LABEL: @test_vabsduw
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| ; CHECK: vabsduw 2, 2, 3
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| ; CHECK: blr
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| }
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