251 lines
8.0 KiB
LLVM
251 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test the doubleword comparison expansions on Power7
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;
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
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define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
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; CHECK-LABEL: v2si64_cmp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vperm 3, 2, 2, 3
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; CHECK-NEXT: xxland 34, 35, 34
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: v2si64_cmp:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: vcmpequw 2, 2, 3
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; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-BE-NEXT: lxvw4x 35, 0, 3
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; CHECK-BE-NEXT: vperm 3, 2, 2, 3
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; CHECK-BE-NEXT: xxland 34, 35, 34
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; CHECK-BE-NEXT: blr
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%cmp = icmp eq <2 x i64> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %result
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}
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; Greater than signed
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define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
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; CHECK-LABEL: v2si64_cmp_gt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxswapd 0, 35
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; CHECK-NEXT: addi 3, 1, -32
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; CHECK-NEXT: addi 4, 1, -48
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; CHECK-NEXT: xxswapd 1, 34
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; CHECK-NEXT: stxvd2x 0, 0, 3
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; CHECK-NEXT: stxvd2x 1, 0, 4
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; CHECK-NEXT: ld 3, -24(1)
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; CHECK-NEXT: ld 4, -40(1)
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; CHECK-NEXT: ld 6, -48(1)
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; CHECK-NEXT: cmpd 4, 3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, -1
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; CHECK-NEXT: iselgt 5, 4, 3
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; CHECK-NEXT: std 5, -8(1)
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; CHECK-NEXT: ld 5, -32(1)
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; CHECK-NEXT: cmpd 6, 5
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: std 3, -16(1)
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; CHECK-NEXT: addi 3, 1, -16
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 34, 0
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: v2si64_cmp_gt:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: addi 3, 1, -32
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; CHECK-BE-NEXT: addi 4, 1, -48
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; CHECK-BE-NEXT: stxvd2x 35, 0, 3
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; CHECK-BE-NEXT: stxvd2x 34, 0, 4
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; CHECK-BE-NEXT: ld 3, -24(1)
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; CHECK-BE-NEXT: ld 4, -40(1)
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; CHECK-BE-NEXT: ld 6, -48(1)
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; CHECK-BE-NEXT: cmpd 4, 3
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; CHECK-BE-NEXT: li 3, 0
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; CHECK-BE-NEXT: li 4, -1
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; CHECK-BE-NEXT: iselgt 5, 4, 3
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; CHECK-BE-NEXT: std 5, -8(1)
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; CHECK-BE-NEXT: ld 5, -32(1)
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; CHECK-BE-NEXT: cmpd 6, 5
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; CHECK-BE-NEXT: iselgt 3, 4, 3
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; CHECK-BE-NEXT: std 3, -16(1)
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; CHECK-BE-NEXT: addi 3, 1, -16
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; CHECK-BE-NEXT: lxvd2x 34, 0, 3
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; CHECK-BE-NEXT: blr
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%cmp = icmp sgt <2 x i64> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %result
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}
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; Greater than unsigned
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define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
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; CHECK-LABEL: v2ui64_cmp_gt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxswapd 0, 35
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; CHECK-NEXT: addi 3, 1, -32
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; CHECK-NEXT: addi 4, 1, -48
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; CHECK-NEXT: xxswapd 1, 34
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; CHECK-NEXT: stxvd2x 0, 0, 3
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; CHECK-NEXT: stxvd2x 1, 0, 4
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; CHECK-NEXT: ld 3, -24(1)
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; CHECK-NEXT: ld 4, -40(1)
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; CHECK-NEXT: ld 6, -48(1)
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; CHECK-NEXT: cmpld 4, 3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, -1
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; CHECK-NEXT: iselgt 5, 4, 3
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; CHECK-NEXT: std 5, -8(1)
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; CHECK-NEXT: ld 5, -32(1)
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; CHECK-NEXT: cmpld 6, 5
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: std 3, -16(1)
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; CHECK-NEXT: addi 3, 1, -16
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 34, 0
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: v2ui64_cmp_gt:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: addi 3, 1, -32
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; CHECK-BE-NEXT: addi 4, 1, -48
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; CHECK-BE-NEXT: stxvd2x 35, 0, 3
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; CHECK-BE-NEXT: stxvd2x 34, 0, 4
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; CHECK-BE-NEXT: ld 3, -24(1)
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; CHECK-BE-NEXT: ld 4, -40(1)
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; CHECK-BE-NEXT: ld 6, -48(1)
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; CHECK-BE-NEXT: cmpld 4, 3
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; CHECK-BE-NEXT: li 3, 0
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; CHECK-BE-NEXT: li 4, -1
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; CHECK-BE-NEXT: iselgt 5, 4, 3
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; CHECK-BE-NEXT: std 5, -8(1)
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; CHECK-BE-NEXT: ld 5, -32(1)
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; CHECK-BE-NEXT: cmpld 6, 5
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; CHECK-BE-NEXT: iselgt 3, 4, 3
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; CHECK-BE-NEXT: std 3, -16(1)
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; CHECK-BE-NEXT: addi 3, 1, -16
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; CHECK-BE-NEXT: lxvd2x 34, 0, 3
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; CHECK-BE-NEXT: blr
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%cmp = icmp ugt <2 x i64> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %result
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}
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; Check the intrinsics also
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declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
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define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: test_vcmpequd_p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: xxlxor 35, 35, 35
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; CHECK-NEXT: xxsldwi 0, 34, 34, 1
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; CHECK-NEXT: xxland 0, 0, 34
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; CHECK-NEXT: xxspltw 1, 0, 2
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xxmrghd 34, 0, 1
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; CHECK-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-NEXT: mfocrf 3, 2
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; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vcmpequd_p:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: vcmpequw 2, 2, 3
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; CHECK-BE-NEXT: xxlxor 35, 35, 35
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; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 1
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; CHECK-BE-NEXT: xxland 0, 0, 34
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; CHECK-BE-NEXT: xxspltw 1, 0, 2
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; CHECK-BE-NEXT: xxspltw 0, 0, 0
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; CHECK-BE-NEXT: xxmrghd 34, 0, 1
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; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-BE-NEXT: mfocrf 3, 2
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; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-BE-NEXT: blr
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%tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
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ret i32 %tmp
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}
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define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: test_vcmpgtsd_p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcmpgtuw 4, 2, 3
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; CHECK-NEXT: vcmpequw 5, 2, 3
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; CHECK-NEXT: vcmpgtsw 2, 2, 3
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; CHECK-NEXT: xxlxor 35, 35, 35
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; CHECK-NEXT: xxsldwi 0, 36, 36, 1
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; CHECK-NEXT: xxland 0, 0, 37
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; CHECK-NEXT: xxlor 0, 34, 0
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; CHECK-NEXT: xxspltw 1, 0, 2
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xxmrghd 34, 0, 1
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; CHECK-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-NEXT: mfocrf 3, 2
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; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vcmpgtsd_p:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3
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; CHECK-BE-NEXT: vcmpequw 5, 2, 3
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; CHECK-BE-NEXT: vcmpgtsw 2, 2, 3
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; CHECK-BE-NEXT: xxlxor 35, 35, 35
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; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1
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; CHECK-BE-NEXT: xxland 0, 0, 37
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; CHECK-BE-NEXT: xxlor 0, 34, 0
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; CHECK-BE-NEXT: xxspltw 1, 0, 2
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; CHECK-BE-NEXT: xxspltw 0, 0, 0
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; CHECK-BE-NEXT: xxmrghd 34, 0, 1
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; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-BE-NEXT: mfocrf 3, 2
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; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-BE-NEXT: blr
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%tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
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ret i32 %tmp
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}
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define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: test_vcmpgtud_p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcmpgtuw 4, 2, 3
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: xxlxor 35, 35, 35
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; CHECK-NEXT: xxsldwi 0, 36, 36, 1
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; CHECK-NEXT: xxland 0, 0, 34
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; CHECK-NEXT: xxlor 0, 36, 0
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; CHECK-NEXT: xxspltw 1, 0, 2
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xxmrghd 34, 0, 1
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; CHECK-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-NEXT: mfocrf 3, 2
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; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vcmpgtud_p:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3
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; CHECK-BE-NEXT: vcmpequw 2, 2, 3
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; CHECK-BE-NEXT: xxlxor 35, 35, 35
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; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1
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; CHECK-BE-NEXT: xxland 0, 0, 34
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; CHECK-BE-NEXT: xxlor 0, 36, 0
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; CHECK-BE-NEXT: xxspltw 1, 0, 2
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; CHECK-BE-NEXT: xxspltw 0, 0, 0
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; CHECK-BE-NEXT: xxmrghd 34, 0, 1
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; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3
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; CHECK-BE-NEXT: mfocrf 3, 2
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; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-BE-NEXT: blr
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%tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y)
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ret i32 %tmp
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}
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