439 lines
11 KiB
LLVM
439 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
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; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
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; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
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define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
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; CHECK-LABEL: bittest_7_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 128
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%shr = lshr i32 %a, 7
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
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; CHECK-LABEL: bittest_10_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1024
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%shr = lshr i32 %a, 10
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
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; NOZBS-LABEL: bittest_11_i32:
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; NOZBS: # %bb.0:
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; NOZBS-NEXT: srli a0, a0, 11
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; NOZBS-NEXT: not a0, a0
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; NOZBS-NEXT: andi a0, a0, 1
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; NOZBS-NEXT: ret
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;
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; ZBS-LABEL: bittest_11_i32:
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; ZBS: # %bb.0:
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; ZBS-NEXT: bexti a0, a0, 11
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; ZBS-NEXT: xori a0, a0, 1
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; ZBS-NEXT: ret
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%shr = lshr i32 %a, 11
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
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; RV32-LABEL: bittest_31_i32:
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; RV32: # %bb.0:
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; RV32-NEXT: not a0, a0
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; RV32-NEXT: srli a0, a0, 31
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bittest_31_i32:
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; RV64: # %bb.0:
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; RV64-NEXT: not a0, a0
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; RV64-NEXT: srliw a0, a0, 31
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; RV64-NEXT: ret
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%shr = lshr i32 %a, 31
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define i64 @bittest_7_i64(i64 %a) nounwind {
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; RV32-LABEL: bittest_7_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a0, a0, 128
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bittest_7_i64:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, 128
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%shr = lshr i64 %a, 7
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_10_i64(i64 %a) nounwind {
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; RV32-LABEL: bittest_10_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a0, a0, 1024
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bittest_10_i64:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, 1024
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%shr = lshr i64 %a, 10
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_11_i64(i64 %a) nounwind {
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; RV32I-LABEL: bittest_11_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 11
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: bittest_11_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 11
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV32ZBS-LABEL: bittest_11_i64:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: bexti a0, a0, 11
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; RV32ZBS-NEXT: xori a0, a0, 1
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; RV32ZBS-NEXT: li a1, 0
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; RV32ZBS-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_11_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 11
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 11
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_31_i64(i64 %a) nounwind {
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; RV32-LABEL: bittest_31_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: not a0, a0
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; RV32-NEXT: srli a0, a0, 31
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64I-LABEL: bittest_31_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 31
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_31_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 31
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 31
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_32_i64(i64 %a) nounwind {
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; RV32-LABEL: bittest_32_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: not a0, a1
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64I-LABEL: bittest_32_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_32_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 32
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 32
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_63_i64(i64 %a) nounwind {
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; RV32-LABEL: bittest_63_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: not a0, a1
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; RV32-NEXT: srli a0, a0, 31
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bittest_63_i64:
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; RV64: # %bb.0:
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; RV64-NEXT: not a0, a0
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; RV64-NEXT: srli a0, a0, 63
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; RV64-NEXT: ret
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%shr = lshr i64 %a, 63
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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; Make sure we use (andi (srl X, Y), 1) or bext.
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define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind {
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; RV32I-LABEL: bittest_constant_by_var_shr_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 301408
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; RV32I-NEXT: addi a1, a1, 722
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; RV32I-NEXT: srl a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: bittest_constant_by_var_shr_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 301408
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; RV64I-NEXT: addiw a1, a1, 722
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; RV64I-NEXT: srlw a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV32ZBS-LABEL: bittest_constant_by_var_shr_i32:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: lui a1, 301408
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; RV32ZBS-NEXT: addi a1, a1, 722
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; RV32ZBS-NEXT: bext a0, a1, a0
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; RV32ZBS-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: lui a1, 301408
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; RV64ZBS-NEXT: addiw a1, a1, 722
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; RV64ZBS-NEXT: bext a0, a1, a0
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; RV64ZBS-NEXT: ret
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%shl = lshr i32 1234567890, %b
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%and = and i32 %shl, 1
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%cmp = icmp ne i32 %and, 0
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ret i1 %cmp
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}
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; Make sure we use (andi (srl X, Y), 1) or bext.
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define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {
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; RV32I-LABEL: bittest_constant_by_var_shl_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 301408
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; RV32I-NEXT: addi a1, a1, 722
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; RV32I-NEXT: srl a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: bittest_constant_by_var_shl_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 301408
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; RV64I-NEXT: addiw a1, a1, 722
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; RV64I-NEXT: srlw a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV32ZBS-LABEL: bittest_constant_by_var_shl_i32:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: lui a1, 301408
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; RV32ZBS-NEXT: addi a1, a1, 722
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; RV32ZBS-NEXT: bext a0, a1, a0
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; RV32ZBS-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: lui a1, 301408
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; RV64ZBS-NEXT: addiw a1, a1, 722
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; RV64ZBS-NEXT: bext a0, a1, a0
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; RV64ZBS-NEXT: ret
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%shl = shl i32 1, %b
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%and = and i32 %shl, 1234567890
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%cmp = icmp ne i32 %and, 0
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ret i1 %cmp
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}
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; Make sure we use (andi (srl X, Y), 1) or bext.
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define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
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; RV32-LABEL: bittest_constant_by_var_shr_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi a1, a0, -32
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; RV32-NEXT: bltz a1, .LBB12_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: andi a0, zero, 1
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB12_2:
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; RV32-NEXT: lui a1, 301408
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; RV32-NEXT: addi a1, a1, 722
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; RV32-NEXT: srl a0, a1, a0
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: ret
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;
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; RV64I-LABEL: bittest_constant_by_var_shr_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 301408
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; RV64I-NEXT: addiw a1, a1, 722
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; RV64I-NEXT: srl a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: lui a1, 301408
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; RV64ZBS-NEXT: addiw a1, a1, 722
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; RV64ZBS-NEXT: bext a0, a1, a0
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; RV64ZBS-NEXT: ret
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%shl = lshr i64 1234567890, %b
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%and = and i64 %shl, 1
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%cmp = icmp ne i64 %and, 0
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ret i1 %cmp
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}
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; Make sure we use (andi (srl X, Y), 1) or bext.
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define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
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; RV32-LABEL: bittest_constant_by_var_shl_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi a1, a0, -32
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; RV32-NEXT: bltz a1, .LBB13_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: andi a0, zero, 1
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB13_2:
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; RV32-NEXT: lui a1, 301408
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; RV32-NEXT: addi a1, a1, 722
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; RV32-NEXT: srl a0, a1, a0
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: ret
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;
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; RV64I-LABEL: bittest_constant_by_var_shl_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 301408
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; RV64I-NEXT: addiw a1, a1, 722
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; RV64I-NEXT: srl a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: lui a1, 301408
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; RV64ZBS-NEXT: addiw a1, a1, 722
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; RV64ZBS-NEXT: bext a0, a1, a0
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; RV64ZBS-NEXT: ret
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%shl = shl i64 1, %b
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%and = and i64 %shl, 1234567890
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%cmp = icmp ne i64 %and, 0
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ret i1 %cmp
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}
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; We want to use (andi (srl X, Y), 1) or bext before the beqz.
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define void @bittest_switch(i32 signext %0) {
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; RV32I-LABEL: bittest_switch:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a1, 31
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; RV32I-NEXT: bltu a1, a0, .LBB14_3
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: lui a1, 524291
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; RV32I-NEXT: addi a1, a1, 768
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; RV32I-NEXT: srl a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: beqz a0, .LBB14_3
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; RV32I-NEXT: # %bb.2:
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; RV32I-NEXT: tail bar@plt
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; RV32I-NEXT: .LBB14_3:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: bittest_switch:
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; RV64I: # %bb.0:
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; RV64I-NEXT: li a1, 31
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; RV64I-NEXT: bltu a1, a0, .LBB14_3
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: lui a1, 2048
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; RV64I-NEXT: addiw a1, a1, 51
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: srl a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: beqz a0, .LBB14_3
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; RV64I-NEXT: # %bb.2:
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; RV64I-NEXT: tail bar@plt
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; RV64I-NEXT: .LBB14_3:
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; RV64I-NEXT: ret
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;
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; RV32ZBS-LABEL: bittest_switch:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: li a1, 31
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; RV32ZBS-NEXT: bltu a1, a0, .LBB14_3
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; RV32ZBS-NEXT: # %bb.1:
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; RV32ZBS-NEXT: lui a1, 524291
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; RV32ZBS-NEXT: addi a1, a1, 768
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; RV32ZBS-NEXT: bext a0, a1, a0
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; RV32ZBS-NEXT: beqz a0, .LBB14_3
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; RV32ZBS-NEXT: # %bb.2:
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; RV32ZBS-NEXT: tail bar@plt
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; RV32ZBS-NEXT: .LBB14_3:
|
|
; RV32ZBS-NEXT: ret
|
|
;
|
|
; RV64ZBS-LABEL: bittest_switch:
|
|
; RV64ZBS: # %bb.0:
|
|
; RV64ZBS-NEXT: li a1, 31
|
|
; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3
|
|
; RV64ZBS-NEXT: # %bb.1:
|
|
; RV64ZBS-NEXT: lui a1, 2048
|
|
; RV64ZBS-NEXT: addiw a1, a1, 51
|
|
; RV64ZBS-NEXT: slli a1, a1, 8
|
|
; RV64ZBS-NEXT: bext a0, a1, a0
|
|
; RV64ZBS-NEXT: beqz a0, .LBB14_3
|
|
; RV64ZBS-NEXT: # %bb.2:
|
|
; RV64ZBS-NEXT: tail bar@plt
|
|
; RV64ZBS-NEXT: .LBB14_3:
|
|
; RV64ZBS-NEXT: ret
|
|
switch i32 %0, label %3 [
|
|
i32 8, label %2
|
|
i32 9, label %2
|
|
i32 12, label %2
|
|
i32 13, label %2
|
|
i32 31, label %2
|
|
]
|
|
|
|
2:
|
|
tail call void @bar()
|
|
br label %3
|
|
|
|
3:
|
|
ret void
|
|
}
|
|
|
|
declare void @bar()
|