49 lines
2.2 KiB
LLVM
49 lines
2.2 KiB
LLVM
; This test is designed to run three times, once with function attributes, once
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; with all target attributes added on the command line, and once with compress
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; added with the command line and float added via function attributes, all
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; three of these should result in the same output.
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;
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; RUN: cat %s > %t.tgtattr
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; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
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; RUN: -disable-block-placement < %t.tgtattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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;
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; RUN: cat %s > %t.fnattr
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; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \
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; RUN: -disable-block-placement < %t.fnattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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;
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; RUN: cat %s > %t.mixedattr
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; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \
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; RUN: -disable-block-placement < %t.mixedattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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; This acts as a basic correctness check for the codegen instruction compression
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; path, verifying that the assembled file contains compressed instructions when
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; expected. Handling of the compressed ISA is implemented so the same
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; transformation patterns should be used whether compressing an input .s file or
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; compressing codegen output. This file contains basic functionality tests using
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; instructions which also require one of the floating point extensions.
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define float @float_load(float *%a) #0 {
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; RV32IFDC-LABEL: <float_load>:
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; RV32IFDC: c.flw fa0, 0(a0)
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; RV32IFDC-NEXT: c.jr ra
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%1 = load volatile float, float* %a
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ret float %1
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}
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define double @double_load(double *%a) #0 {
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; RV32IFDC-LABEL: <double_load>:
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; RV32IFDC: c.fld fa0, 0(a0)
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; RV32IFDC-NEXT: c.jr ra
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%1 = load volatile double, double* %a
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ret double %1
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}
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