1160 lines
34 KiB
LLVM
1160 lines
34 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
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; RUN: -verify-machineinstrs -target-abi=ilp32f \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=ilp32f \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
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; RUN: -verify-machineinstrs -target-abi=lp64f \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=lp64d \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
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; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
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; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
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declare float @llvm.sqrt.f32(float)
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define float @sqrt_f32(float %a) nounwind {
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; RV32IF-LABEL: sqrt_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsqrt.s fa0, fa0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: sqrt_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsqrt.s fa0, fa0
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: sqrt_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call sqrtf@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sqrt_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call sqrtf@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.sqrt.f32(float %a)
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ret float %1
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}
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declare float @llvm.powi.f32.i32(float, i32)
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define float @powi_f32(float %a, i32 %b) nounwind {
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; RV32IF-LABEL: powi_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call __powisf2@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: powi_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: sext.w a0, a0
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; RV64IF-NEXT: call __powisf2@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: powi_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __powisf2@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: powi_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: call __powisf2@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
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ret float %1
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}
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declare float @llvm.sin.f32(float)
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define float @sin_f32(float %a) nounwind {
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; RV32IF-LABEL: sin_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call sinf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: sin_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call sinf@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: sin_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call sinf@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sin_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call sinf@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.sin.f32(float %a)
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ret float %1
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}
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declare float @llvm.cos.f32(float)
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define float @cos_f32(float %a) nounwind {
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; RV32IF-LABEL: cos_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call cosf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: cos_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call cosf@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: cos_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call cosf@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cos_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call cosf@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.cos.f32(float %a)
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ret float %1
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}
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; The sin+cos combination results in an FSINCOS SelectionDAG node.
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define float @sincos_f32(float %a) nounwind {
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; RV32IF-LABEL: sincos_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fmv.s fs0, fa0
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; RV32IF-NEXT: call sinf@plt
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; RV32IF-NEXT: fmv.s fs1, fa0
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; RV32IF-NEXT: fmv.s fa0, fs0
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; RV32IF-NEXT: call cosf@plt
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; RV32IF-NEXT: fadd.s fa0, fs1, fa0
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV32I-LABEL: sincos_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: call sinf@plt
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: mv a0, s0
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; RV32I-NEXT: call cosf@plt
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: mv a0, s1
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; RV32I-NEXT: call __addsf3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sincos_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv s0, a0
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; RV64I-NEXT: call sinf@plt
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; RV64I-NEXT: mv s1, a0
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: call cosf@plt
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: mv a0, s1
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; RV64I-NEXT: call __addsf3@plt
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; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: ret
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%1 = call float @llvm.sin.f32(float %a)
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%2 = call float @llvm.cos.f32(float %a)
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%3 = fadd float %1, %2
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ret float %3
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}
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declare float @llvm.pow.f32(float, float)
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define float @pow_f32(float %a, float %b) nounwind {
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; RV32IF-LABEL: pow_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call powf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: pow_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call powf@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: pow_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call powf@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pow_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call powf@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.pow.f32(float %a, float %b)
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ret float %1
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}
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declare float @llvm.exp.f32(float)
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define float @exp_f32(float %a) nounwind {
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; RV32IF-LABEL: exp_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call expf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: exp_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call expf@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: exp_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call expf@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: exp_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call expf@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.exp.f32(float %a)
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ret float %1
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}
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declare float @llvm.exp2.f32(float)
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define float @exp2_f32(float %a) nounwind {
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; RV32IF-LABEL: exp2_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call exp2f@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: exp2_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call exp2f@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: exp2_f32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call exp2f@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: exp2_f32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call exp2f@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.exp2.f32(float %a)
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ret float %1
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}
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declare float @llvm.log.f32(float)
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define float @log_f32(float %a) nounwind {
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; RV32IF-LABEL: log_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call logf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: log_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call logf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: log_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call logf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: log_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call logf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.log.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.log10.f32(float)
|
|
|
|
define float @log10_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: log10_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call log10f@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: log10_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call log10f@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: log10_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call log10f@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: log10_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call log10f@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.log10.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.log2.f32(float)
|
|
|
|
define float @log2_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: log2_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call log2f@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: log2_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call log2f@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: log2_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call log2f@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: log2_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call log2f@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.log2.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.fma.f32(float, float, float)
|
|
|
|
define float @fma_f32(float %a, float %b, float %c) nounwind {
|
|
; RV32IF-LABEL: fma_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fma_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: fma_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call fmaf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: fma_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call fmaf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.fmuladd.f32(float, float, float)
|
|
|
|
define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
|
|
; RV32IF-LABEL: fmuladd_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fmuladd_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: fmuladd_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: mv s0, a2
|
|
; RV32I-NEXT: call __mulsf3@plt
|
|
; RV32I-NEXT: mv a1, s0
|
|
; RV32I-NEXT: call __addsf3@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: fmuladd_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: mv s0, a2
|
|
; RV64I-NEXT: call __mulsf3@plt
|
|
; RV64I-NEXT: mv a1, s0
|
|
; RV64I-NEXT: call __addsf3@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.fabs.f32(float)
|
|
|
|
define float @fabs_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: fabs_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fabs.s fa0, fa0
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fabs_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fabs.s fa0, fa0
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: fabs_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 1
|
|
; RV32I-NEXT: srli a0, a0, 1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: fabs_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 33
|
|
; RV64I-NEXT: srli a0, a0, 33
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.fabs.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.minnum.f32(float, float)
|
|
|
|
define float @minnum_f32(float %a, float %b) nounwind {
|
|
; RV32IF-LABEL: minnum_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmin.s fa0, fa0, fa1
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: minnum_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: minnum_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call fminf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: minnum_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call fminf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.minnum.f32(float %a, float %b)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.maxnum.f32(float, float)
|
|
|
|
define float @maxnum_f32(float %a, float %b) nounwind {
|
|
; RV32IF-LABEL: maxnum_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmax.s fa0, fa0, fa1
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: maxnum_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmax.s fa0, fa0, fa1
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: maxnum_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call fmaxf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: maxnum_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call fmaxf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.maxnum.f32(float %a, float %b)
|
|
ret float %1
|
|
}
|
|
|
|
; TODO: FMINNAN and FMAXNAN aren't handled in
|
|
; SelectionDAGLegalize::ExpandNode.
|
|
|
|
; declare float @llvm.minimum.f32(float, float)
|
|
|
|
; define float @fminimum_f32(float %a, float %b) nounwind {
|
|
; %1 = call float @llvm.minimum.f32(float %a, float %b)
|
|
; ret float %1
|
|
; }
|
|
|
|
; declare float @llvm.maximum.f32(float, float)
|
|
|
|
; define float @fmaximum_f32(float %a, float %b) nounwind {
|
|
; %1 = call float @llvm.maximum.f32(float %a, float %b)
|
|
; ret float %1
|
|
; }
|
|
|
|
declare float @llvm.copysign.f32(float, float)
|
|
|
|
define float @copysign_f32(float %a, float %b) nounwind {
|
|
; RV32IF-LABEL: copysign_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: copysign_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: copysign_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a2, 524288
|
|
; RV32I-NEXT: and a1, a1, a2
|
|
; RV32I-NEXT: slli a0, a0, 1
|
|
; RV32I-NEXT: srli a0, a0, 1
|
|
; RV32I-NEXT: or a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: copysign_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a2, 524288
|
|
; RV64I-NEXT: and a1, a1, a2
|
|
; RV64I-NEXT: slli a0, a0, 33
|
|
; RV64I-NEXT: srli a0, a0, 33
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.copysign.f32(float %a, float %b)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.floor.f32(float)
|
|
|
|
define float @floor_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: floor_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call floorf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: floor_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call floorf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: floor_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call floorf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: floor_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call floorf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.floor.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.ceil.f32(float)
|
|
|
|
define float @ceil_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: ceil_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call ceilf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: ceil_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call ceilf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: ceil_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call ceilf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: ceil_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call ceilf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.ceil.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.trunc.f32(float)
|
|
|
|
define float @trunc_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: trunc_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call truncf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: trunc_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call truncf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: trunc_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call truncf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: trunc_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call truncf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.trunc.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.rint.f32(float)
|
|
|
|
define float @rint_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: rint_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call rintf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: rint_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call rintf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: rint_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call rintf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: rint_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call rintf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.rint.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.nearbyint.f32(float)
|
|
|
|
define float @nearbyint_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: nearbyint_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call nearbyintf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: nearbyint_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call nearbyintf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: nearbyint_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call nearbyintf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: nearbyint_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call nearbyintf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.nearbyint.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.round.f32(float)
|
|
|
|
define float @round_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: round_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call roundf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: round_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call roundf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: round_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call roundf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: round_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call roundf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.round.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare float @llvm.roundeven.f32(float)
|
|
|
|
define float @roundeven_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: roundeven_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call roundevenf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: roundeven_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: addi sp, sp, -16
|
|
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IF-NEXT: call roundevenf@plt
|
|
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IF-NEXT: addi sp, sp, 16
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: roundeven_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call roundevenf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: roundeven_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call roundevenf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call float @llvm.roundeven.f32(float %a)
|
|
ret float %1
|
|
}
|
|
|
|
declare iXLen @llvm.lrint.iXLen.f32(float)
|
|
|
|
define iXLen @lrint_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: lrint_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fcvt.w.s a0, fa0
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: lrint_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fcvt.l.s a0, fa0
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: lrint_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call lrintf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: lrint_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call lrintf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call iXLen @llvm.lrint.iXLen.f32(float %a)
|
|
ret iXLen %1
|
|
}
|
|
|
|
declare iXLen @llvm.lround.iXLen.f32(float)
|
|
|
|
define iXLen @lround_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: lround_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: lround_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: lround_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call lroundf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: lround_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call lroundf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call iXLen @llvm.lround.iXLen.f32(float %a)
|
|
ret iXLen %1
|
|
}
|
|
|
|
declare i64 @llvm.llrint.i64.f32(float)
|
|
|
|
define i64 @llrint_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: llrint_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call llrintf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: llrint_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fcvt.l.s a0, fa0
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: llrint_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call llrintf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: llrint_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call llrintf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call i64 @llvm.llrint.i64.f32(float %a)
|
|
ret i64 %1
|
|
}
|
|
|
|
declare i64 @llvm.llround.i64.f32(float)
|
|
|
|
define i64 @llround_f32(float %a) nounwind {
|
|
; RV32IF-LABEL: llround_f32:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: addi sp, sp, -16
|
|
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IF-NEXT: call llroundf@plt
|
|
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IF-NEXT: addi sp, sp, 16
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: llround_f32:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
|
|
; RV64IF-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: llround_f32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32I-NEXT: call llroundf@plt
|
|
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: llround_f32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64I-NEXT: call llroundf@plt
|
|
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = call i64 @llvm.llround.i64.f32(float %a)
|
|
ret i64 %1
|
|
}
|