232 lines
6.3 KiB
LLVM
232 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i686-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=X86
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; Make sure that flags are properly preserved despite atomic optimizations.
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define i32 @atomic_and_flags_1(i8* %p, i32 %a, i32 %b) {
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; X64-LABEL: atomic_and_flags_1:
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; X64: # %bb.0:
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; X64-NEXT: cmpl %edx, %esi
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; X64-NEXT: jne .LBB0_3
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; X64-NEXT: # %bb.1: # %L1
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; X64-NEXT: incb (%rdi)
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; X64-NEXT: cmpl %edx, %esi
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; X64-NEXT: jne .LBB0_2
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; X64-NEXT: # %bb.4: # %L3
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; X64-NEXT: movl $3, %eax
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; X64-NEXT: retq
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; X64-NEXT: .LBB0_3: # %L2
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; X64-NEXT: movl $2, %eax
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; X64-NEXT: retq
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; X64-NEXT: .LBB0_2: # %L4
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; X64-NEXT: movl $4, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: atomic_and_flags_1:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: jne .LBB0_3
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; X86-NEXT: # %bb.1: # %L1
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: incb (%edx)
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: jne .LBB0_2
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; X86-NEXT: # %bb.4: # %L3
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; X86-NEXT: movl $3, %eax
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; X86-NEXT: retl
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; X86-NEXT: .LBB0_3: # %L2
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; X86-NEXT: movl $2, %eax
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; X86-NEXT: retl
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; X86-NEXT: .LBB0_2: # %L4
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; X86-NEXT: movl $4, %eax
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; X86-NEXT: retl
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; Generate flags value, and use it.
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %L1, label %L2
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L1:
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; The following pattern will get folded.
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%1 = load atomic i8, i8* %p seq_cst, align 1
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%2 = add i8 %1, 1 ; This forces the INC instruction to be generated.
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store atomic i8 %2, i8* %p release, align 1
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; Use the comparison result again. We need to rematerialize the comparison
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; somehow. This test checks that cmpl gets emitted again, but any
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; rematerialization would work (the optimizer used to clobber the flags with
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; the add).
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br i1 %cmp, label %L3, label %L4
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L2:
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ret i32 2
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L3:
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ret i32 3
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L4:
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ret i32 4
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}
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; Same as above, but using 2 as immediate to avoid the INC instruction.
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define i32 @atomic_and_flags_2(i8* %p, i32 %a, i32 %b) {
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; X64-LABEL: atomic_and_flags_2:
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; X64: # %bb.0:
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; X64-NEXT: cmpl %edx, %esi
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; X64-NEXT: jne .LBB1_3
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; X64-NEXT: # %bb.1: # %L1
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; X64-NEXT: addb $2, (%rdi)
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; X64-NEXT: cmpl %edx, %esi
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; X64-NEXT: jne .LBB1_2
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; X64-NEXT: # %bb.4: # %L3
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; X64-NEXT: movl $3, %eax
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; X64-NEXT: retq
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; X64-NEXT: .LBB1_3: # %L2
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; X64-NEXT: movl $2, %eax
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; X64-NEXT: retq
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; X64-NEXT: .LBB1_2: # %L4
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; X64-NEXT: movl $4, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: atomic_and_flags_2:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: jne .LBB1_3
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; X86-NEXT: # %bb.1: # %L1
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: addb $2, (%edx)
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: jne .LBB1_2
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; X86-NEXT: # %bb.4: # %L3
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; X86-NEXT: movl $3, %eax
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; X86-NEXT: retl
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; X86-NEXT: .LBB1_3: # %L2
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; X86-NEXT: movl $2, %eax
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; X86-NEXT: retl
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; X86-NEXT: .LBB1_2: # %L4
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; X86-NEXT: movl $4, %eax
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; X86-NEXT: retl
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %L1, label %L2
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L1:
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%1 = load atomic i8, i8* %p seq_cst, align 1
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%2 = add i8 %1, 2
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store atomic i8 %2, i8* %p release, align 1
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br i1 %cmp, label %L3, label %L4
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L2:
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ret i32 2
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L3:
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ret i32 3
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L4:
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ret i32 4
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}
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; PR20841 - ensure we don't reuse the ZF flag from XADD for compares with zero,
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; the flags are set for the result of the add result (the value stored to memory),
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; not the value returned by the atomicrmw add.
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define zeroext i1 @xadd_cmp0_i64(i64* %x) nounwind {
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; X64-LABEL: xadd_cmp0_i64:
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; X64: # %bb.0:
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; X64-NEXT: movl $1, %eax
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; X64-NEXT: lock xaddq %rax, (%rdi)
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; X64-NEXT: testq %rax, %rax
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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;
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; X86-LABEL: xadd_cmp0_i64:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl (%esi), %eax
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; X86-NEXT: movl 4(%esi), %edx
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; X86-NEXT: .p2align 4, 0x90
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; X86-NEXT: .LBB2_1: # %atomicrmw.start
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; X86-NEXT: # =>This Inner Loop Header: Depth=1
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; X86-NEXT: movl %eax, %ebx
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; X86-NEXT: addl $1, %ebx
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; X86-NEXT: movl %edx, %ecx
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; X86-NEXT: adcl $0, %ecx
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; X86-NEXT: lock cmpxchg8b (%esi)
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; X86-NEXT: jne .LBB2_1
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; X86-NEXT: # %bb.2: # %atomicrmw.end
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; X86-NEXT: orl %edx, %eax
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; X86-NEXT: sete %al
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl
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%add = atomicrmw add i64* %x, i64 1 seq_cst
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%cmp = icmp eq i64 %add, 0
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ret i1 %cmp
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}
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define zeroext i1 @xadd_cmp0_i32(i32* %x) nounwind {
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; X64-LABEL: xadd_cmp0_i32:
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; X64: # %bb.0:
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; X64-NEXT: movl $1, %eax
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; X64-NEXT: lock xaddl %eax, (%rdi)
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; X64-NEXT: testl %eax, %eax
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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;
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; X86-LABEL: xadd_cmp0_i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl $1, %ecx
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; X86-NEXT: lock xaddl %ecx, (%eax)
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; X86-NEXT: testl %ecx, %ecx
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; X86-NEXT: setne %al
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; X86-NEXT: retl
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%add = atomicrmw add i32* %x, i32 1 seq_cst
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%cmp = icmp ne i32 %add, 0
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ret i1 %cmp
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}
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define zeroext i1 @xadd_cmp0_i16(i16* %x) nounwind {
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; X64-LABEL: xadd_cmp0_i16:
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; X64: # %bb.0:
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; X64-NEXT: movw $1, %ax
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; X64-NEXT: lock xaddw %ax, (%rdi)
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; X64-NEXT: testw %ax, %ax
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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;
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; X86-LABEL: xadd_cmp0_i16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movw $1, %cx
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; X86-NEXT: lock xaddw %cx, (%eax)
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; X86-NEXT: testw %cx, %cx
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; X86-NEXT: sete %al
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; X86-NEXT: retl
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%add = atomicrmw add i16* %x, i16 1 seq_cst
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%cmp = icmp eq i16 %add, 0
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ret i1 %cmp
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}
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define zeroext i1 @xadd_cmp0_i8(i8* %x) nounwind {
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; X64-LABEL: xadd_cmp0_i8:
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; X64: # %bb.0:
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; X64-NEXT: movb $1, %al
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; X64-NEXT: lock xaddb %al, (%rdi)
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; X64-NEXT: testb %al, %al
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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;
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; X86-LABEL: xadd_cmp0_i8:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movb $1, %cl
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; X86-NEXT: lock xaddb %cl, (%eax)
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; X86-NEXT: testb %cl, %cl
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; X86-NEXT: setne %al
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; X86-NEXT: retl
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%add = atomicrmw add i8* %x, i8 1 seq_cst
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%cmp = icmp ne i8 %add, 0
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ret i1 %cmp
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}
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