48 lines
2.3 KiB
LLVM
48 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX
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define <16 x i8> @test_v16i8_nosignbit(<16 x i8> %a, <16 x i8> %b) {
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; SSE2-LABEL: test_v16i8_nosignbit:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: pmaxub %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_v16i8_nosignbit:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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; SSE41-NEXT: pand %xmm2, %xmm0
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; SSE41-NEXT: pand %xmm1, %xmm2
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; SSE41-NEXT: pmaxsb %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; SSE42-LABEL: test_v16i8_nosignbit:
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; SSE42: # %bb.0:
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; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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; SSE42-NEXT: pand %xmm2, %xmm0
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; SSE42-NEXT: pand %xmm1, %xmm2
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; SSE42-NEXT: pmaxsb %xmm2, %xmm0
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: test_v16i8_nosignbit:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
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; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = and <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
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%2 = and <16 x i8> %b, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
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%3 = icmp sgt <16 x i8> %1, %2
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%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
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ret <16 x i8> %4
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}
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