136 lines
5.0 KiB
LLVM
136 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX
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declare i32 @llvm.ssub.sat.i32 (i32, i32)
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declare i64 @llvm.ssub.sat.i64 (i64, i64)
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declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
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; fold (ssub_sat x, undef) -> 0
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define i32 @combine_undef_i32(i32 %a0) {
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; CHECK-LABEL: combine_undef_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%res = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 undef)
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ret i32 %res
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}
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define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
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; SSE-LABEL: combine_undef_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_undef_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
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ret <8 x i16> %res
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}
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; fold (ssub_sat c1, c2) -> c3
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define i32 @combine_constfold_i32() {
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; CHECK-LABEL: combine_constfold_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-2147483547, %eax # imm = 0x80000065
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; CHECK-NEXT: retq
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%res = call i32 @llvm.ssub.sat.i32(i32 100, i32 2147483647)
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ret i32 %res
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}
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define <8 x i16> @combine_constfold_v8i16() {
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; SSE-LABEL: combine_constfold_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,2,254,0,65534,65282,32786,2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_constfold_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,2,254,0,65534,65282,32786,2]
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)
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ret <8 x i16> %res
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}
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define <8 x i16> @combine_constfold_undef_v8i16() {
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; SSE-LABEL: combine_constfold_undef_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65534,65282,32786,2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_constfold_undef_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65534,65282,32786,2]
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)
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ret <8 x i16> %res
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}
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; fold (ssub_sat x, 0) -> x
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define i32 @combine_zero_i32(i32 %a0) {
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; CHECK-LABEL: combine_zero_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 0)
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ret i32 %1
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}
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define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {
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; CHECK-LABEL: combine_zero_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)
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ret <8 x i16> %1
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}
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; fold (ssub_sat x, x) -> 0
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define i32 @combine_self_i32(i32 %a0) {
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; CHECK-LABEL: combine_self_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 %a0)
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ret i32 %1
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}
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define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
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; SSE-LABEL: combine_self_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_self_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
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ret <8 x i16> %1
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}
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; fold (ssub_sat (shuffle x, u, m), (shuffle y, u, m)) -> (shuffle (ssub_sat x, y), u, m)
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define <8 x i16> @combine_shuffle_shuffle_v8i16(<8 x i16> %x0, <8 x i16> %y0) {
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; SSE-LABEL: combine_shuffle_shuffle_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: psubsw %xmm1, %xmm0
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; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_shuffle_shuffle_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsubsw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; AVX-NEXT: retq
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%x1= shufflevector <8 x i16> %x0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
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%y1 = shufflevector <8 x i16> %y0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
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%res = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x1, <8 x i16> %y1)
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ret <8 x i16> %res
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}
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