455 lines
14 KiB
LLVM
455 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; fold (sub x, 0) -> x
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define <4 x i32> @combine_vec_sub_zero(<4 x i32> %a) {
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; CHECK-LABEL: combine_vec_sub_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = sub <4 x i32> %a, zeroinitializer
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ret <4 x i32> %1
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}
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; fold (sub x, x) -> 0
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define <4 x i32> @combine_vec_sub_self(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_self:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_self:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, %a
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ret <4 x i32> %1
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}
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; fold (sub x, c) -> (add x, -c)
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define <4 x i32> @combine_vec_sub_constant(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_constant:
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; SSE: # %bb.0:
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; SSE-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_constant:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %1
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}
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; Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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define <4 x i32> @combine_vec_sub_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_negone:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_negone:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
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ret <4 x i32> %1
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}
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; fold A-(A-B) -> B
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define <4 x i32> @combine_vec_sub_sub(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: combine_vec_sub_sub:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sub:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %a, %b
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%2 = sub <4 x i32> %a, %1
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ret <4 x i32> %2
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}
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; fold (A+B)-A -> B
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define <4 x i32> @combine_vec_sub_add0(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: combine_vec_sub_add0:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add0:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %a, %b
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%2 = sub <4 x i32> %1, %a
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ret <4 x i32> %2
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}
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; fold (A+B)-B -> A
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define <4 x i32> @combine_vec_sub_add1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: combine_vec_sub_add1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = add <4 x i32> %a, %b
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%2 = sub <4 x i32> %1, %b
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ret <4 x i32> %2
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}
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; fold C2-(A+C1) -> (C2-C1)-A
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define <4 x i32> @combine_vec_sub_constant_add(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_sub_constant_add:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_constant_add:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %a, <i32 0, i32 1, i32 2, i32 3>
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%2 = sub <4 x i32> <i32 3, i32 2, i32 1, i32 0>, %1
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ret <4 x i32> %2
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}
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; fold ((A+(B+C))-B) -> A+C
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define <4 x i32> @combine_vec_sub_add_add(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_add_add:
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; SSE: # %bb.0:
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; SSE-NEXT: paddd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add_add:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %b, %c
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%2 = add <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %b
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ret <4 x i32> %3
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}
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; fold ((A+(B-C))-B) -> A-C
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define <4 x i32> @combine_vec_sub_add_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_add_sub:
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; SSE: # %bb.0:
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_add_sub:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %b, %c
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%2 = add <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %b
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ret <4 x i32> %3
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}
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; fold ((A-(B-C))-C) -> A-B
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define <4 x i32> @combine_vec_sub_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_vec_sub_sub_sub:
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; SSE: # %bb.0:
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sub_sub:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sub <4 x i32> %b, %c
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%2 = sub <4 x i32> %a, %1
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%3 = sub <4 x i32> %2, %c
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ret <4 x i32> %3
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}
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; fold undef-A -> undef
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define <4 x i32> @combine_vec_sub_undef0(<4 x i32> %a) {
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; CHECK-LABEL: combine_vec_sub_undef0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = sub <4 x i32> undef, %a
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ret <4 x i32> %1
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}
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; fold A-undef -> undef
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define <4 x i32> @combine_vec_sub_undef1(<4 x i32> %a) {
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; CHECK-LABEL: combine_vec_sub_undef1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = sub <4 x i32> %a, undef
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ret <4 x i32> %1
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}
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; sub X, (sext Y i1) -> add X, (and Y 1)
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define <4 x i32> @combine_vec_add_sext(<4 x i32> %x, <4 x i1> %y) {
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; SSE-LABEL: combine_vec_add_sext:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_add_sext:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sext <4 x i1> %y to <4 x i32>
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%2 = sub <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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; sub X, (sextinreg Y i1) -> add X, (and Y 1)
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define <4 x i32> @combine_vec_sub_sextinreg(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_sub_sextinreg:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_sextinreg:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %y, <i32 31, i32 31, i32 31, i32 31>
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%2 = ashr <4 x i32> %1, <i32 31, i32 31, i32 31, i32 31>
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%3 = sub <4 x i32> %x, %2
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ret <4 x i32> %3
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}
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; sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1
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define i32 @combine_sub_xor_consts(i32 %x) {
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; CHECK-LABEL: combine_sub_xor_consts:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: xorl $-32, %edi
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; CHECK-NEXT: leal 33(%rdi), %eax
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; CHECK-NEXT: retq
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%xor = xor i32 %x, 31
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%sub = sub i32 32, %xor
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ret i32 %sub
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}
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define <4 x i32> @combine_vec_sub_xor_consts(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_xor_consts:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sub_xor_consts:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%xor = xor <4 x i32> %x, <i32 28, i32 29, i32 -1, i32 -31>
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%sub = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %xor
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ret <4 x i32> %sub
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}
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define <4 x i32> @combine_vec_neg_xor_consts(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_neg_xor_consts:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_neg_xor_consts:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%xor = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%sub = sub <4 x i32> zeroinitializer, %xor
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ret <4 x i32> %sub
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}
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; With AVX, this could use broadcast (an extra load) and
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; load-folded 'add', but currently we favor the virtually
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; free pcmpeq instruction.
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define void @PR52032_oneuse_constant(<8 x i32>* %p) {
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; SSE-LABEL: PR52032_oneuse_constant:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqu (%rdi), %xmm0
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; SSE-NEXT: movdqu 16(%rdi), %xmm1
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; SSE-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE-NEXT: psubd %xmm2, %xmm1
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: movdqu %xmm0, (%rdi)
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; SSE-NEXT: movdqu %xmm1, 16(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR52032_oneuse_constant:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqu (%rdi), %ymm0
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; AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
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; AVX-NEXT: vpsubd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vmovdqu %ymm0, (%rdi)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%i3 = load <8 x i32>, <8 x i32>* %p, align 4
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%i4 = add nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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store <8 x i32> %i4, <8 x i32>* %p, align 4
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ret void
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}
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; With AVX, we don't transform 'add' to 'sub' because that prevents load folding.
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; With SSE, we do it because we can't load fold the other op without overwriting the constant op.
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define void @PR52032(<8 x i32>* %p) {
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; SSE-LABEL: PR52032:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: movdqu (%rdi), %xmm1
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; SSE-NEXT: movdqu 16(%rdi), %xmm2
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; SSE-NEXT: movdqu 32(%rdi), %xmm3
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; SSE-NEXT: movdqu 48(%rdi), %xmm4
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; SSE-NEXT: psubd %xmm0, %xmm2
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqu %xmm1, (%rdi)
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; SSE-NEXT: movdqu %xmm2, 16(%rdi)
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; SSE-NEXT: psubd %xmm0, %xmm4
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; SSE-NEXT: psubd %xmm0, %xmm3
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; SSE-NEXT: movdqu %xmm3, 32(%rdi)
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; SSE-NEXT: movdqu %xmm4, 48(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR52032:
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; AVX: # %bb.0:
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; AVX-NEXT: vpbroadcastd {{.*#+}} ymm0 = [1,1,1,1,1,1,1,1]
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; AVX-NEXT: vpaddd (%rdi), %ymm0, %ymm1
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; AVX-NEXT: vmovdqu %ymm1, (%rdi)
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; AVX-NEXT: vpaddd 32(%rdi), %ymm0, %ymm0
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; AVX-NEXT: vmovdqu %ymm0, 32(%rdi)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%i3 = load <8 x i32>, <8 x i32>* %p, align 4
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%i4 = add nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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store <8 x i32> %i4, <8 x i32>* %p, align 4
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%p2 = getelementptr inbounds <8 x i32>, <8 x i32>* %p, i64 1
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%i8 = load <8 x i32>, <8 x i32>* %p2, align 4
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%i9 = add nsw <8 x i32> %i8, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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store <8 x i32> %i9, <8 x i32>* %p2, align 4
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ret void
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}
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; Same as above, but 128-bit ops:
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; With AVX, we don't transform 'add' to 'sub' because that prevents load folding.
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; With SSE, we do it because we can't load fold the other op without overwriting the constant op.
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define void @PR52032_2(<4 x i32>* %p) {
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; SSE-LABEL: PR52032_2:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: movdqu (%rdi), %xmm1
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; SSE-NEXT: movdqu 16(%rdi), %xmm2
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqu %xmm1, (%rdi)
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; SSE-NEXT: psubd %xmm0, %xmm2
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; SSE-NEXT: movdqu %xmm2, 16(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR52032_2:
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; AVX: # %bb.0:
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; AVX-NEXT: vpbroadcastd {{.*#+}} xmm0 = [1,1,1,1]
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; AVX-NEXT: vpaddd (%rdi), %xmm0, %xmm1
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; AVX-NEXT: vmovdqu %xmm1, (%rdi)
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; AVX-NEXT: vpaddd 16(%rdi), %xmm0, %xmm0
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; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)
|
|
; AVX-NEXT: retq
|
|
%i3 = load <4 x i32>, <4 x i32>* %p, align 4
|
|
%i4 = add nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i4, <4 x i32>* %p, align 4
|
|
%p2 = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i64 1
|
|
%i8 = load <4 x i32>, <4 x i32>* %p2, align 4
|
|
%i9 = add nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i9, <4 x i32>* %p2, align 4
|
|
ret void
|
|
}
|
|
|
|
; If we are starting with a 'sub', it is always better to do the transform.
|
|
|
|
define void @PR52032_3(<4 x i32>* %p) {
|
|
; SSE-LABEL: PR52032_3:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
|
|
; SSE-NEXT: movdqu (%rdi), %xmm1
|
|
; SSE-NEXT: movdqu 16(%rdi), %xmm2
|
|
; SSE-NEXT: paddd %xmm0, %xmm1
|
|
; SSE-NEXT: movdqu %xmm1, (%rdi)
|
|
; SSE-NEXT: paddd %xmm0, %xmm2
|
|
; SSE-NEXT: movdqu %xmm2, 16(%rdi)
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: PR52032_3:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: vpaddd (%rdi), %xmm0, %xmm1
|
|
; AVX-NEXT: vmovdqu %xmm1, (%rdi)
|
|
; AVX-NEXT: vpaddd 16(%rdi), %xmm0, %xmm0
|
|
; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)
|
|
; AVX-NEXT: retq
|
|
%i3 = load <4 x i32>, <4 x i32>* %p, align 4
|
|
%i4 = sub nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i4, <4 x i32>* %p, align 4
|
|
%p2 = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i64 1
|
|
%i8 = load <4 x i32>, <4 x i32>* %p2, align 4
|
|
%i9 = sub nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i9, <4 x i32>* %p2, align 4
|
|
ret void
|
|
}
|
|
|
|
; If there's no chance of profitable load folding (because of extra uses), we convert 'add' to 'sub'.
|
|
|
|
define void @PR52032_4(<4 x i32>* %p, <4 x i32>* %q) {
|
|
; SSE-LABEL: PR52032_4:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movdqu (%rdi), %xmm0
|
|
; SSE-NEXT: movdqa %xmm0, (%rsi)
|
|
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
|
|
; SSE-NEXT: psubd %xmm1, %xmm0
|
|
; SSE-NEXT: movdqu %xmm0, (%rdi)
|
|
; SSE-NEXT: movdqu 16(%rdi), %xmm0
|
|
; SSE-NEXT: movdqa %xmm0, 16(%rsi)
|
|
; SSE-NEXT: psubd %xmm1, %xmm0
|
|
; SSE-NEXT: movdqu %xmm0, 16(%rdi)
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: PR52032_4:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vmovdqu (%rdi), %xmm0
|
|
; AVX-NEXT: vmovdqa %xmm0, (%rsi)
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: vmovdqu %xmm0, (%rdi)
|
|
; AVX-NEXT: vmovdqu 16(%rdi), %xmm0
|
|
; AVX-NEXT: vmovdqa %xmm0, 16(%rsi)
|
|
; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)
|
|
; AVX-NEXT: retq
|
|
%i3 = load <4 x i32>, <4 x i32>* %p, align 4
|
|
store <4 x i32> %i3, <4 x i32>* %q
|
|
%i4 = add nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i4, <4 x i32>* %p, align 4
|
|
%p2 = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i64 1
|
|
%q2 = getelementptr inbounds <4 x i32>, <4 x i32>* %q, i64 1
|
|
%i8 = load <4 x i32>, <4 x i32>* %p2, align 4
|
|
store <4 x i32> %i8, <4 x i32>* %q2
|
|
%i9 = add nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>
|
|
store <4 x i32> %i9, <4 x i32>* %p2, align 4
|
|
ret void
|
|
}
|