53 lines
2.1 KiB
LLVM
53 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 -O0 < %s | FileCheck %s
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; Check that at -O0, the backend doesn't attempt to canonicalize a vector load
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; used by an INSERTPS into a scalar load plus scalar_to_vector.
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;
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; In order to fold a load into the memory operand of an INSERTPSrm, the backend
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; tries to canonicalize a vector load in input to an INSERTPS node into a
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; scalar load plus scalar_to_vector. This would allow ISel to match the
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; INSERTPSrm variant rather than a load plus INSERTPSrr.
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;
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; However, ISel can only select an INSERTPSrm if folding a load into the operand
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; of an insertps is considered to be profitable.
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;
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; In the example below:
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;
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; __m128 test(__m128 a, __m128 *b) {
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; __m128 c = _mm_insert_ps(a, *b, 1 << 6);
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; return c;
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; }
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;
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; At -O0, the backend would attempt to canonicalize the load to 'b' into
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; a scalar load in the hope of matching an INSERTPSrm.
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; However, ISel would fail to recognize an INSERTPSrm since load folding is
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; always considered unprofitable at -O0. This would leave the insertps mask
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; in an invalid state.
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;
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; The problem with the canonicalization rule performed by the backend is that
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; it assumes ISel to always be able to match an INSERTPSrm. This assumption is
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; not always correct at -O0. In this example, FastISel fails to lower the
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; arguments needed by the entry block. This is enough to enable the DAGCombiner
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; and eventually trigger the canonicalization on the INSERTPS node.
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;
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; This test checks that the vector load in input to the insertps is not
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; canonicalized into a scalar load plus scalar_to_vector (a movss).
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define <4 x float> @test(<4 x float> %a, <4 x float>* %b) {
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; CHECK-LABEL: test:
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; CHECK: movaps (%rdi), [[REG:%[a-z0-9]+]]
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; CHECK-NOT: movss
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; CHECK: insertps $64, [[REG]],
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; CHECK: ret
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entry:
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%0 = load <4 x float>, <4 x float>* %b, align 16
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%1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %0, i32 64)
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%2 = alloca <4 x float>, align 16
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store <4 x float> %1, <4 x float>* %2, align 16
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%3 = load <4 x float>, <4 x float>* %2, align 16
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ret <4 x float> %3
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32)
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