87 lines
2.7 KiB
LLVM
87 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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;
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; This test makes sure that InstCombine does not replace the sequence of
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; xor/sub instruction followed by cmp instruction into a single cmp instruction
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; if there is more than one use of xor/sub.
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define zeroext i1 @test1(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]]
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; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[SEL]]
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;
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%xor = xor i32 %lhs, 5
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%cmp1 = icmp eq i32 %xor, 10
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%cmp2 = icmp eq i32 %xor, %rhs
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%sel = or i1 %cmp1, %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test1_logical(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test1_logical(
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; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]]
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
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; CHECK-NEXT: ret i1 [[SEL]]
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;
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%xor = xor i32 %lhs, 5
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%cmp1 = icmp eq i32 %xor, 10
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%cmp2 = icmp eq i32 %xor, %rhs
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%sel = select i1 %cmp1, i1 true, i1 %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test2(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], [[RHS:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 0
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], 32
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; CHECK-NEXT: [[SEL:%.*]] = xor i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[SEL]]
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;
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%xor = xor i32 %lhs, %rhs
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%cmp1 = icmp eq i32 %xor, 0
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%cmp2 = icmp eq i32 %xor, 32
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%sel = xor i1 %cmp1, %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test3(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[LHS:%.*]], [[RHS:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SUB]], 31
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; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[SEL]]
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;
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%sub = sub nsw i32 %lhs, %rhs
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%cmp1 = icmp eq i32 %sub, 0
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%cmp2 = icmp eq i32 %sub, 31
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%sel = or i1 %cmp1, %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test3_logical(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test3_logical(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[LHS:%.*]], [[RHS:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SUB]], 31
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
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; CHECK-NEXT: ret i1 [[SEL]]
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;
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%sub = sub nsw i32 %lhs, %rhs
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%cmp1 = icmp eq i32 %sub, 0
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%cmp2 = icmp eq i32 %sub, 31
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%sel = select i1 %cmp1, i1 true, i1 %cmp2
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ret i1 %sel
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}
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