llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
Philip Reames f7bb691d61 [RISCV] Implement isElementTypeLegalForScalableVector TTI hook
This brings us into alignment with AArch64, and in the process fixes a compiler crash bug in uniform store handling in the vectorizer.

Before the recent invalid cost bailout work, this would have also avoided crashes on invalid costs in some cases. I honestly think the vectorizer should gracefully bailout on uniform stores it can't use a scatter for, but it doesn't, so lets take the path of least resistance here. It's also possible that there are other vectorizer bugs AArch64 isn't seeing because of this hook; we don't want to be finding them either.

Differential Revision: https://reviews.llvm.org/D127514
2022-06-10 13:20:58 -07:00
..
illegal-type.ll [RISCV] Implement isElementTypeLegalForScalableVector TTI hook 2022-06-10 13:20:58 -07:00
lit.local.cfg
low-trip-count.ll [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors 2022-05-16 09:14:24 +01:00
masked_gather_scatter.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
reg-usage.ll [RISCV] Define risc-v's own register class to model FP Register. 2022-06-06 14:43:52 +08:00
riscv-interleaved.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
riscv-unroll.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
riscv-vector-reverse.ll [RISCV] Add cost model for reverse shuffle 2022-06-09 07:21:40 -07:00
scalable-reductions.ll Revert "[NFCI] Regenerate SROA/LoopVectorize test checks" 2022-04-04 01:15:30 +02:00
scalable-vf-hint.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
unroll-in-loop-vectorizer.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00