47 lines
1.8 KiB
YAML
47 lines
1.8 KiB
YAML
# REQUIRES: amdgpu-registered-target
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# RUN: llvm-reduce -abort-on-invalid-reduction -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
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# Verify that reduction works with generic virtual registers, and the
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# properties like register banks, types and names.
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# CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
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# CHECK-INTERESTINGNESS: G_BITCAST
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# CHECK-INTERESTINGNESS: G_ADD
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# CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
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# CHECK-INTERESTINGNESS: G_STORE
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# RESULT: %{{[0-9]+}}:vgpr(s32) = G_IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:vgpr(<2 x s16>) = G_IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:sgpr(p1) = G_IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:vreg_64(s64) = IMPLICIT_DEF
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# RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_IMPLICIT_DEF
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# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %14(<2 x s32>)
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# RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
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# RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
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# RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1)
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# RESULT-NEXT: S_ENDPGM 0{{$}}
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---
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name: f
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
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%v0:vgpr(s32) = COPY $vgpr0
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%v1:vgpr(<2 x s16>) = COPY $vgpr1
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%unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF
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%unused_load:_(s64) = G_LOAD %unused_load_ptr :: (load (s64), addrspace 1)
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G_STORE %unused_load, %unused_load_ptr :: (store (s64), addrspace 1)
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%2:vreg_64(s64) = COPY $vgpr2_vgpr3
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%arst:_(<2 x s32>) = G_IMPLICIT_DEF
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%aoeu:_(s64) = G_BITCAST %arst
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S_NOP 0
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%add:_(s64) = G_ADD %aoeu, %aoeu
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%ptr:_(p1) = G_IMPLICIT_DEF
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G_STORE %v0, %ptr :: (store 4, addrspace 1)
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S_ENDPGM 0, implicit %add, implicit %v1, implicit %2
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...
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