488 lines
17 KiB
C++
488 lines
17 KiB
C++
//===- VarLenCodeEmitterGen.cpp - CEG for variable-length insts -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The CodeEmitterGen component for variable-length instructions.
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//
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// The basic CodeEmitterGen is almost exclusively designed for fixed-
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// length instructions. A good analogy for its encoding scheme is how printf
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// works: The (immutable) formatting string represent the fixed values in the
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// encoded instruction. Placeholders (i.e. %something), on the other hand,
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// represent encoding for instruction operands.
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// ```
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// printf("1101 %src 1001 %dst", <encoded value for operand `src`>,
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// <encoded value for operand `dst`>);
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// ```
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// VarLenCodeEmitterGen in this file provides an alternative encoding scheme
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// that works more like a C++ stream operator:
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// ```
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// OS << 0b1101;
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// if (Cond)
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// OS << OperandEncoding0;
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// OS << 0b1001 << OperandEncoding1;
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// ```
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// You are free to concatenate arbitrary types (and sizes) of encoding
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// fragments on any bit position, bringing more flexibilities on defining
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// encoding for variable-length instructions.
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//
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// In a more specific way, instruction encoding is represented by a DAG type
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// `Inst` field. Here is an example:
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// ```
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// dag Inst = (descend 0b1101, (operand "$src", 4), 0b1001,
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// (operand "$dst", 4));
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// ```
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// It represents the following instruction encoding:
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// ```
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// MSB LSB
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// 1101<encoding for operand src>1001<encoding for operand dst>
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// ```
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// For more details about DAG operators in the above snippet, please
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// refer to \file include/llvm/Target/Target.td.
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//
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// VarLenCodeEmitter will convert the above DAG into the same helper function
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// generated by CodeEmitter, `MCCodeEmitter::getBinaryCodeForInstr` (except
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// for few details).
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//
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//===----------------------------------------------------------------------===//
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#include "VarLenCodeEmitterGen.h"
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#include "CodeGenHwModes.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "InfoByHwMode.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Error.h"
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using namespace llvm;
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namespace {
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class VarLenCodeEmitterGen {
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RecordKeeper &Records;
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DenseMap<Record *, VarLenInst> VarLenInsts;
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// Emit based values (i.e. fixed bits in the encoded instructions)
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void emitInstructionBaseValues(
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raw_ostream &OS,
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ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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CodeGenTarget &Target, int HwMode = -1);
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std::string getInstructionCase(Record *R, CodeGenTarget &Target);
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std::string getInstructionCaseForEncoding(Record *R, Record *EncodingDef,
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CodeGenTarget &Target);
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public:
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explicit VarLenCodeEmitterGen(RecordKeeper &R) : Records(R) {}
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void run(raw_ostream &OS);
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};
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} // end anonymous namespace
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VarLenInst::VarLenInst(const DagInit *DI, const RecordVal *TheDef)
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: TheDef(TheDef), NumBits(0U) {
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buildRec(DI);
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for (const auto &S : Segments)
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NumBits += S.BitWidth;
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}
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void VarLenInst::buildRec(const DagInit *DI) {
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assert(TheDef && "The def record is nullptr ?");
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std::string Op = DI->getOperator()->getAsString();
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if (Op == "ascend" || Op == "descend") {
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bool Reverse = Op == "descend";
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int i = Reverse ? DI->getNumArgs() - 1 : 0;
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int e = Reverse ? -1 : DI->getNumArgs();
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int s = Reverse ? -1 : 1;
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for (; i != e; i += s) {
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const Init *Arg = DI->getArg(i);
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if (const auto *BI = dyn_cast<BitsInit>(Arg)) {
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if (!BI->isComplete())
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PrintFatalError(TheDef->getLoc(),
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"Expecting complete bits init in `" + Op + "`");
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Segments.push_back({BI->getNumBits(), BI});
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} else if (const auto *BI = dyn_cast<BitInit>(Arg)) {
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if (!BI->isConcrete())
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PrintFatalError(TheDef->getLoc(),
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"Expecting concrete bit init in `" + Op + "`");
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Segments.push_back({1, BI});
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} else if (const auto *SubDI = dyn_cast<DagInit>(Arg)) {
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buildRec(SubDI);
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} else {
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PrintFatalError(TheDef->getLoc(), "Unrecognized type of argument in `" +
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Op + "`: " + Arg->getAsString());
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}
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}
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} else if (Op == "operand") {
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// (operand <operand name>, <# of bits>, [(encoder <custom encoder>)])
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if (DI->getNumArgs() < 2)
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PrintFatalError(TheDef->getLoc(),
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"Expecting at least 2 arguments for `operand`");
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HasDynamicSegment = true;
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const Init *OperandName = DI->getArg(0), *NumBits = DI->getArg(1);
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if (!isa<StringInit>(OperandName) || !isa<IntInit>(NumBits))
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PrintFatalError(TheDef->getLoc(), "Invalid argument types for `operand`");
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auto NumBitsVal = cast<IntInit>(NumBits)->getValue();
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if (NumBitsVal <= 0)
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PrintFatalError(TheDef->getLoc(), "Invalid number of bits for `operand`");
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StringRef CustomEncoder;
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if (DI->getNumArgs() >= 3)
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CustomEncoder = getCustomEncoderName(DI->getArg(2));
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Segments.push_back(
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{static_cast<unsigned>(NumBitsVal), OperandName, CustomEncoder});
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} else if (Op == "slice") {
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// (slice <operand name>, <high / low bit>, <low / high bit>,
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// [(encoder <custom encoder>)])
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if (DI->getNumArgs() < 3)
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PrintFatalError(TheDef->getLoc(),
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"Expecting at least 3 arguments for `slice`");
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HasDynamicSegment = true;
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Init *OperandName = DI->getArg(0), *HiBit = DI->getArg(1),
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*LoBit = DI->getArg(2);
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if (!isa<StringInit>(OperandName) || !isa<IntInit>(HiBit) ||
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!isa<IntInit>(LoBit))
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PrintFatalError(TheDef->getLoc(), "Invalid argument types for `slice`");
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auto HiBitVal = cast<IntInit>(HiBit)->getValue(),
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LoBitVal = cast<IntInit>(LoBit)->getValue();
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if (HiBitVal < 0 || LoBitVal < 0)
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PrintFatalError(TheDef->getLoc(), "Invalid bit range for `slice`");
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bool NeedSwap = false;
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unsigned NumBits = 0U;
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if (HiBitVal < LoBitVal) {
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NeedSwap = true;
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NumBits = static_cast<unsigned>(LoBitVal - HiBitVal + 1);
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} else {
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NumBits = static_cast<unsigned>(HiBitVal - LoBitVal + 1);
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}
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StringRef CustomEncoder;
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if (DI->getNumArgs() >= 4)
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CustomEncoder = getCustomEncoderName(DI->getArg(3));
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if (NeedSwap) {
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// Normalization: Hi bit should always be the second argument.
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Init *const NewArgs[] = {OperandName, LoBit, HiBit};
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Segments.push_back({NumBits,
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DagInit::get(DI->getOperator(), nullptr, NewArgs, {}),
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CustomEncoder});
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} else {
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Segments.push_back({NumBits, DI, CustomEncoder});
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}
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}
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}
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void VarLenCodeEmitterGen::run(raw_ostream &OS) {
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CodeGenTarget Target(Records);
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auto Insts = Records.getAllDerivedDefinitions("Instruction");
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auto NumberedInstructions = Target.getInstructionsByEnumValue();
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const CodeGenHwModes &HWM = Target.getHwModes();
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// The set of HwModes used by instruction encodings.
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std::set<unsigned> HwModes;
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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// Create the corresponding VarLenInst instance.
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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for (auto &KV : EBM) {
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HwModes.insert(KV.first);
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Record *EncodingDef = KV.second;
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RecordVal *RV = EncodingDef->getValue("Inst");
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DagInit *DI = cast<DagInit>(RV->getValue());
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VarLenInsts.insert({EncodingDef, VarLenInst(DI, RV)});
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}
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continue;
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}
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}
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RecordVal *RV = R->getValue("Inst");
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DagInit *DI = cast<DagInit>(RV->getValue());
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VarLenInsts.insert({R, VarLenInst(DI, RV)});
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}
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// Emit function declaration
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OS << "void " << Target.getName()
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<< "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
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<< " SmallVectorImpl<MCFixup> &Fixups,\n"
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<< " APInt &Inst,\n"
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<< " APInt &Scratch,\n"
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<< " const MCSubtargetInfo &STI) const {\n";
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// Emit instruction base values
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if (HwModes.empty()) {
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emitInstructionBaseValues(OS, NumberedInstructions, Target);
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} else {
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for (unsigned HwMode : HwModes)
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emitInstructionBaseValues(OS, NumberedInstructions, Target, (int)HwMode);
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}
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if (!HwModes.empty()) {
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OS << " const unsigned **Index;\n";
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OS << " const uint64_t *InstBits;\n";
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OS << " unsigned HwMode = STI.getHwMode();\n";
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OS << " switch (HwMode) {\n";
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OS << " default: llvm_unreachable(\"Unknown hardware mode!\"); break;\n";
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for (unsigned I : HwModes) {
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OS << " case " << I << ": InstBits = InstBits_" << HWM.getMode(I).Name
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<< "; Index = Index_" << HWM.getMode(I).Name << "; break;\n";
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}
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OS << " };\n";
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}
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// Emit helper function to retrieve base values.
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OS << " auto getInstBits = [&](unsigned Opcode) -> APInt {\n"
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<< " unsigned NumBits = Index[Opcode][0];\n"
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<< " if (!NumBits)\n"
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<< " return APInt::getZeroWidth();\n"
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<< " unsigned Idx = Index[Opcode][1];\n"
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<< " ArrayRef<uint64_t> Data(&InstBits[Idx], "
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<< "APInt::getNumWords(NumBits));\n"
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<< " return APInt(NumBits, Data);\n"
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<< " };\n";
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// Map to accumulate all the cases.
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std::map<std::string, std::vector<std::string>> CaseMap;
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// Construct all cases statement for each opcode
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for (Record *R : Insts) {
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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std::string InstName =
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(R->getValueAsString("Namespace") + "::" + R->getName()).str();
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std::string Case = getInstructionCase(R, Target);
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CaseMap[Case].push_back(std::move(InstName));
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}
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// Emit initial function code
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OS << " const unsigned opcode = MI.getOpcode();\n"
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<< " switch (opcode) {\n";
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// Emit each case statement
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for (const auto &C : CaseMap) {
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const std::string &Case = C.first;
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const auto &InstList = C.second;
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ListSeparator LS("\n");
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for (const auto &InstName : InstList)
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OS << LS << " case " << InstName << ":";
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OS << " {\n";
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OS << Case;
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OS << " break;\n"
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<< " }\n";
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}
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// Default case: unhandled opcode
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OS << " default:\n"
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<< " std::string msg;\n"
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<< " raw_string_ostream Msg(msg);\n"
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<< " Msg << \"Not supported instr: \" << MI;\n"
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<< " report_fatal_error(Msg.str().c_str());\n"
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<< " }\n";
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OS << "}\n\n";
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}
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static void emitInstBits(raw_ostream &IS, raw_ostream &SS, const APInt &Bits,
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unsigned &Index) {
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if (!Bits.getNumWords()) {
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IS.indent(4) << "{/*NumBits*/0, /*Index*/0},";
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return;
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}
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IS.indent(4) << "{/*NumBits*/" << Bits.getBitWidth() << ", "
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<< "/*Index*/" << Index << "},";
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SS.indent(4);
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for (unsigned I = 0; I < Bits.getNumWords(); ++I, ++Index)
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SS << "UINT64_C(" << utostr(Bits.getRawData()[I]) << "),";
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}
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void VarLenCodeEmitterGen::emitInstructionBaseValues(
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raw_ostream &OS, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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CodeGenTarget &Target, int HwMode) {
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std::string IndexArray, StorageArray;
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raw_string_ostream IS(IndexArray), SS(StorageArray);
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const CodeGenHwModes &HWM = Target.getHwModes();
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if (HwMode == -1) {
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IS << " static const unsigned Index[][2] = {\n";
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SS << " static const uint64_t InstBits[] = {\n";
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} else {
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StringRef Name = HWM.getMode(HwMode).Name;
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IS << " static const unsigned Index_" << Name << "[][2] = {\n";
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SS << " static const uint64_t InstBits_" << Name << "[] = {\n";
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}
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unsigned NumFixedValueWords = 0U;
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo")) {
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IS.indent(4) << "{/*NumBits*/0, /*Index*/0},\n";
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continue;
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}
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Record *EncodingDef = R;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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if (EBM.hasMode(HwMode))
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EncodingDef = EBM.get(HwMode);
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}
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}
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auto It = VarLenInsts.find(EncodingDef);
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if (It == VarLenInsts.end())
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PrintFatalError(EncodingDef, "VarLenInst not found for this record");
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const VarLenInst &VLI = It->second;
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unsigned i = 0U, BitWidth = VLI.size();
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// Start by filling in fixed values.
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APInt Value(BitWidth, 0);
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auto SI = VLI.begin(), SE = VLI.end();
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// Scan through all the segments that have fixed-bits values.
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while (i < BitWidth && SI != SE) {
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unsigned SegmentNumBits = SI->BitWidth;
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if (const auto *BI = dyn_cast<BitsInit>(SI->Value)) {
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for (unsigned Idx = 0U; Idx != SegmentNumBits; ++Idx) {
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auto *B = cast<BitInit>(BI->getBit(Idx));
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Value.setBitVal(i + Idx, B->getValue());
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}
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}
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if (const auto *BI = dyn_cast<BitInit>(SI->Value))
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Value.setBitVal(i, BI->getValue());
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i += SegmentNumBits;
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++SI;
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}
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emitInstBits(IS, SS, Value, NumFixedValueWords);
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IS << '\t' << "// " << R->getName() << "\n";
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if (Value.getNumWords())
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SS << '\t' << "// " << R->getName() << "\n";
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}
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IS.indent(4) << "{/*NumBits*/0, /*Index*/0}\n };\n";
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SS.indent(4) << "UINT64_C(0)\n };\n";
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OS << IS.str() << SS.str();
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}
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std::string VarLenCodeEmitterGen::getInstructionCase(Record *R,
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CodeGenTarget &Target) {
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std::string Case;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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const CodeGenHwModes &HWM = Target.getHwModes();
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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Case += " switch (HwMode) {\n";
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Case += " default: llvm_unreachable(\"Unhandled HwMode\");\n";
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for (auto &KV : EBM) {
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Case += " case " + itostr(KV.first) + ": {\n";
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Case += getInstructionCaseForEncoding(R, KV.second, Target);
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Case += " break;\n";
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Case += " }\n";
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}
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Case += " }\n";
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return Case;
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}
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}
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return getInstructionCaseForEncoding(R, R, Target);
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}
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std::string VarLenCodeEmitterGen::getInstructionCaseForEncoding(
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Record *R, Record *EncodingDef, CodeGenTarget &Target) {
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auto It = VarLenInsts.find(EncodingDef);
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if (It == VarLenInsts.end())
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PrintFatalError(EncodingDef, "Parsed encoding record not found");
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const VarLenInst &VLI = It->second;
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size_t BitWidth = VLI.size();
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CodeGenInstruction &CGI = Target.getInstruction(R);
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std::string Case;
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raw_string_ostream SS(Case);
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// Resize the scratch buffer.
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if (BitWidth && !VLI.isFixedValueOnly())
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SS.indent(6) << "Scratch = Scratch.zext(" << BitWidth << ");\n";
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// Populate based value.
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SS.indent(6) << "Inst = getInstBits(opcode);\n";
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// Process each segment in VLI.
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size_t Offset = 0U;
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for (const auto &ES : VLI) {
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unsigned NumBits = ES.BitWidth;
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const Init *Val = ES.Value;
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// If it's a StringInit or DagInit, it's a reference to an operand
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// or part of an operand.
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if (isa<StringInit>(Val) || isa<DagInit>(Val)) {
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StringRef OperandName;
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unsigned LoBit = 0U;
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if (const auto *SV = dyn_cast<StringInit>(Val)) {
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OperandName = SV->getValue();
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} else {
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// Normalized: (slice <operand name>, <high bit>, <low bit>)
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const auto *DV = cast<DagInit>(Val);
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OperandName = cast<StringInit>(DV->getArg(0))->getValue();
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LoBit = static_cast<unsigned>(cast<IntInit>(DV->getArg(2))->getValue());
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}
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auto OpIdx = CGI.Operands.ParseOperandName(OperandName);
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unsigned FlatOpIdx = CGI.Operands.getFlattenedOperandNumber(OpIdx);
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StringRef CustomEncoder = CGI.Operands[OpIdx.first].EncoderMethodName;
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if (ES.CustomEncoder.size())
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CustomEncoder = ES.CustomEncoder;
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SS.indent(6) << "Scratch.clearAllBits();\n";
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SS.indent(6) << "// op: " << OperandName.drop_front(1) << "\n";
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if (CustomEncoder.empty())
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SS.indent(6) << "getMachineOpValue(MI, MI.getOperand("
|
|
<< utostr(FlatOpIdx) << ")";
|
|
else
|
|
SS.indent(6) << CustomEncoder << "(MI, /*OpIdx=*/" << utostr(FlatOpIdx);
|
|
|
|
SS << ", /*Pos=*/" << utostr(Offset) << ", Scratch, Fixups, STI);\n";
|
|
|
|
SS.indent(6) << "Inst.insertBits("
|
|
<< "Scratch.extractBits(" << utostr(NumBits) << ", "
|
|
<< utostr(LoBit) << ")"
|
|
<< ", " << Offset << ");\n";
|
|
}
|
|
Offset += NumBits;
|
|
}
|
|
|
|
StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
|
|
if (!PostEmitter.empty())
|
|
SS.indent(6) << "Inst = " << PostEmitter << "(MI, Inst, STI);\n";
|
|
|
|
return Case;
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void emitVarLenCodeEmitter(RecordKeeper &R, raw_ostream &OS) {
|
|
VarLenCodeEmitterGen(R).run(OS);
|
|
}
|
|
|
|
} // end namespace llvm
|