Daniel Sanders e4e83a7bc1 [mips] Added support for various EVA ASE instructions. ... Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669		2015-09-15 10:02:16 +00:00
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abiflags.s	Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags	2014-07-14 15:05:51 +00:00
invalid-mips32r2-xfail.s	[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them	2014-05-13 11:45:36 +00:00
invalid-mips32r2.s	[mips] Marked the DI/EI instruction aliases as MIPS32r2	2014-10-16 15:23:52 +00:00
invalid-mips64.s	[mips][msa] Test basic operations for the N32 ABI too.	2015-05-05 08:48:35 +00:00
valid-xfail.s	Revert: r215698 - Current implementation of c.cond.fmt instructions only accept default cc0 register...	2014-08-17 19:47:47 +00:00
valid.s	[mips] Added support for various EVA ASE instructions.	2015-09-15 10:02:16 +00:00