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AArch64
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Reversing the commit in revision 350186. Revision causes regression in 4
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2019-01-01 07:28:55 +00:00 |
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AMDGPU
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[AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression.
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2019-01-03 19:55:32 +00:00 |
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ARC
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…
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ARM
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[ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR.
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2018-12-21 18:07:10 +00:00 |
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AVR
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[AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.
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2019-01-03 21:25:39 +00:00 |
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BPF
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[BPF] Generate BTF DebugInfo under BPF target
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2018-12-19 16:40:25 +00:00 |
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Generic
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Move llc-start-stop-instance to x86
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2018-12-04 18:19:08 +00:00 |
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Hexagon
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[DAGCombiner] allow narrowing of add followed by truncate
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2018-12-22 17:10:31 +00:00 |
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Inputs
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…
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Lanai
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[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
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2018-12-07 12:10:23 +00:00 |
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MIR
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[Dwarf/AArch64] Return address signing B key dwarf support
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2018-12-21 10:45:08 +00:00 |
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MSP430
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[MSP430] Optimize srl/sra in case of A >> (8 + N)
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2018-11-19 10:43:02 +00:00 |
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Mips
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[MIPS GlobalISel] Select G_SELECT
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2018-12-25 14:42:30 +00:00 |
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NVPTX
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Python compat - print statement
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2019-01-03 14:11:33 +00:00 |
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Nios2
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…
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PowerPC
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[Power9] Enable the Out-of-Order scheduling model for P9 hw
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2019-01-03 05:04:18 +00:00 |
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RISCV
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[RISCV] Add support for the various RISC-V FMA instruction variants
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2018-12-13 10:49:05 +00:00 |
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SPARC
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[Sparc] Use float register for integer constrained with "f" in inline asm
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2018-12-13 15:13:29 +00:00 |
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SystemZ
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Pythran compat - range vs. xrange
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2019-01-03 14:11:58 +00:00 |
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Thumb
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[ARM] Complete the Thumb1 shift+and->shift+shift transforms.
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2018-12-20 23:39:54 +00:00 |
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Thumb2
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[ARM] Enable spilling of the hGPR register class in Thumb2
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2018-11-08 13:02:10 +00:00 |
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WebAssembly
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[WebAssembly] Optimize Irreducible Control Flow
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2019-01-03 23:10:11 +00:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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[X86] Add VPSLLI/VPSRLI ((X >>u C1) << C2) SimplifyDemandedBits combine
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2019-01-04 15:43:43 +00:00 |
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XCore
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[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
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2018-12-07 12:10:23 +00:00 |
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