325 lines
10 KiB
C++
325 lines
10 KiB
C++
//===--- HexagonGenMux.cpp ------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// During instruction selection, MUX instructions are generated for
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// conditional assignments. Since such assignments often present an
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// opportunity to predicate instructions, HexagonExpandCondsets
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// expands MUXes into pairs of conditional transfers, and then proceeds
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// with predication of the producers/consumers of the registers involved.
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// This happens after exiting from the SSA form, but before the machine
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// instruction scheduler. After the scheduler and after the register
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// allocation there can be cases of pairs of conditional transfers
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// resulting from a MUX where neither of them was further predicated. If
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// these transfers are now placed far enough from the instruction defining
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// the predicate register, they cannot use the .new form. In such cases it
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// is better to collapse them back to a single MUX instruction.
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#define DEBUG_TYPE "hexmux"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "HexagonTargetMachine.h"
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using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonGenMux();
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void initializeHexagonGenMuxPass(PassRegistry& Registry);
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}
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namespace {
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class HexagonGenMux : public MachineFunctionPass {
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public:
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static char ID;
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HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) {
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initializeHexagonGenMuxPass(*PassRegistry::getPassRegistry());
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}
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const char *getPassName() const override {
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return "Hexagon generate mux instructions";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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const HexagonInstrInfo *HII;
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const HexagonRegisterInfo *HRI;
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struct CondsetInfo {
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unsigned PredR;
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unsigned TrueX, FalseX;
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CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {}
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};
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struct DefUseInfo {
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BitVector Defs, Uses;
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DefUseInfo() : Defs(), Uses() {}
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DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
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};
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struct MuxInfo {
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MachineBasicBlock::iterator At;
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unsigned DefR, PredR;
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MachineOperand *SrcT, *SrcF;
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MachineInstr *Def1, *Def2;
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MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
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MachineOperand *TOp, MachineOperand *FOp, MachineInstr &D1,
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MachineInstr &D2)
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: At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
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Def2(&D2) {}
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};
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typedef DenseMap<MachineInstr*,unsigned> InstrIndexMap;
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typedef DenseMap<unsigned,DefUseInfo> DefUseInfoMap;
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typedef SmallVector<MuxInfo,4> MuxInfoList;
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bool isRegPair(unsigned Reg) const {
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return Hexagon::DoubleRegsRegClass.contains(Reg);
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}
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void getSubRegs(unsigned Reg, BitVector &SRs) const;
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void expandReg(unsigned Reg, BitVector &Set) const;
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void getDefsUses(const MachineInstr *MI, BitVector &Defs,
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BitVector &Uses) const;
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void buildMaps(MachineBasicBlock &B, InstrIndexMap &I2X,
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DefUseInfoMap &DUM);
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bool isCondTransfer(unsigned Opc) const;
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unsigned getMuxOpcode(const MachineOperand &Src1,
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const MachineOperand &Src2) const;
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bool genMuxInBlock(MachineBasicBlock &B);
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};
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char HexagonGenMux::ID = 0;
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}
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INITIALIZE_PASS(HexagonGenMux, "hexagon-mux",
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"Hexagon generate mux instructions", false, false)
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void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
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for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
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SRs[*I] = true;
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}
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void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const {
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if (isRegPair(Reg))
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getSubRegs(Reg, Set);
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else
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Set[Reg] = true;
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}
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void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
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BitVector &Uses) const {
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// First, get the implicit defs and uses for this instruction.
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unsigned Opc = MI->getOpcode();
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const MCInstrDesc &D = HII->get(Opc);
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if (const MCPhysReg *R = D.ImplicitDefs)
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while (*R)
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expandReg(*R++, Defs);
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if (const MCPhysReg *R = D.ImplicitUses)
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while (*R)
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expandReg(*R++, Uses);
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// Look over all operands, and collect explicit defs and uses.
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for (ConstMIOperands Mo(*MI); Mo.isValid(); ++Mo) {
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if (!Mo->isReg() || Mo->isImplicit())
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continue;
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unsigned R = Mo->getReg();
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BitVector &Set = Mo->isDef() ? Defs : Uses;
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expandReg(R, Set);
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}
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}
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void HexagonGenMux::buildMaps(MachineBasicBlock &B, InstrIndexMap &I2X,
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DefUseInfoMap &DUM) {
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unsigned Index = 0;
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unsigned NR = HRI->getNumRegs();
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BitVector Defs(NR), Uses(NR);
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for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
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MachineInstr *MI = &*I;
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I2X.insert(std::make_pair(MI, Index));
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Defs.reset();
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Uses.reset();
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getDefsUses(MI, Defs, Uses);
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DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Uses)));
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Index++;
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}
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}
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bool HexagonGenMux::isCondTransfer(unsigned Opc) const {
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switch (Opc) {
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case Hexagon::A2_tfrt:
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case Hexagon::A2_tfrf:
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case Hexagon::C2_cmoveit:
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case Hexagon::C2_cmoveif:
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return true;
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}
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return false;
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}
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unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
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const MachineOperand &Src2) const {
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bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
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if (IsReg1)
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return IsReg2 ? Hexagon::C2_mux : Hexagon::C2_muxir;
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if (IsReg2)
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return Hexagon::C2_muxri;
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// Neither is a register. The first source is extendable, but the second
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// is not (s8).
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if (Src2.isImm() && isInt<8>(Src2.getImm()))
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return Hexagon::C2_muxii;
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return 0;
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}
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bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
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bool Changed = false;
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InstrIndexMap I2X;
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DefUseInfoMap DUM;
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buildMaps(B, I2X, DUM);
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typedef DenseMap<unsigned,CondsetInfo> CondsetMap;
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CondsetMap CM;
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MuxInfoList ML;
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MachineBasicBlock::iterator NextI, End = B.end();
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for (MachineBasicBlock::iterator I = B.begin(); I != End; I = NextI) {
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MachineInstr *MI = &*I;
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NextI = std::next(I);
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unsigned Opc = MI->getOpcode();
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if (!isCondTransfer(Opc))
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continue;
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unsigned DR = MI->getOperand(0).getReg();
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if (isRegPair(DR))
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continue;
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unsigned PR = MI->getOperand(1).getReg();
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unsigned Idx = I2X.lookup(MI);
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CondsetMap::iterator F = CM.find(DR);
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bool IfTrue = HII->isPredicatedTrue(Opc);
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// If there is no record of a conditional transfer for this register,
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// or the predicate register differs, create a new record for it.
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if (F != CM.end() && F->second.PredR != PR) {
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CM.erase(F);
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F = CM.end();
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}
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if (F == CM.end()) {
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auto It = CM.insert(std::make_pair(DR, CondsetInfo()));
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F = It.first;
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F->second.PredR = PR;
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}
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CondsetInfo &CI = F->second;
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if (IfTrue)
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CI.TrueX = Idx;
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else
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CI.FalseX = Idx;
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if (CI.TrueX == UINT_MAX || CI.FalseX == UINT_MAX)
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continue;
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// There is now a complete definition of DR, i.e. we have the predicate
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// register, the definition if-true, and definition if-false.
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// First, check if both definitions are far enough from the definition
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// of the predicate register.
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unsigned MinX = std::min(CI.TrueX, CI.FalseX);
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unsigned MaxX = std::max(CI.TrueX, CI.FalseX);
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unsigned SearchX = (MaxX > 4) ? MaxX-4 : 0;
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bool NearDef = false;
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for (unsigned X = SearchX; X < MaxX; ++X) {
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const DefUseInfo &DU = DUM.lookup(X);
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if (!DU.Defs[PR])
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continue;
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NearDef = true;
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break;
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}
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if (NearDef)
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continue;
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// The predicate register is not defined in the last few instructions.
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// Check if the conversion to MUX is possible (either "up", i.e. at the
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// place of the earlier partial definition, or "down", where the later
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// definition is located). Examine all defs and uses between these two
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// definitions.
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// SR1, SR2 - source registers from the first and the second definition.
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MachineBasicBlock::iterator It1 = B.begin(), It2 = B.begin();
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std::advance(It1, MinX);
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std::advance(It2, MaxX);
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MachineInstr &Def1 = *It1, &Def2 = *It2;
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MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
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unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
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unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0;
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bool Failure = false, CanUp = true, CanDown = true;
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for (unsigned X = MinX+1; X < MaxX; X++) {
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const DefUseInfo &DU = DUM.lookup(X);
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if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) {
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Failure = true;
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break;
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}
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if (CanDown && DU.Defs[SR1])
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CanDown = false;
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if (CanUp && DU.Defs[SR2])
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CanUp = false;
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}
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if (Failure || (!CanUp && !CanDown))
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continue;
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MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
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MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
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// Prefer "down", since this will move the MUX farther away from the
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// predicate definition.
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MachineBasicBlock::iterator At = CanDown ? Def2 : Def1;
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ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
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}
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for (unsigned I = 0, N = ML.size(); I < N; ++I) {
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MuxInfo &MX = ML[I];
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MachineBasicBlock &B = *MX.At->getParent();
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DebugLoc DL = MX.At->getDebugLoc();
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unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF);
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if (!MxOpc)
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continue;
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BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
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.addReg(MX.PredR)
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.addOperand(*MX.SrcT)
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.addOperand(*MX.SrcF);
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B.erase(MX.Def1);
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B.erase(MX.Def2);
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Changed = true;
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}
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return Changed;
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}
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bool HexagonGenMux::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
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HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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bool Changed = false;
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for (auto &I : MF)
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Changed |= genMuxInBlock(I);
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return Changed;
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}
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FunctionPass *llvm::createHexagonGenMux() {
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return new HexagonGenMux();
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}
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