140 lines
4.7 KiB
C++
140 lines
4.7 KiB
C++
//===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the hazard recognizer for scheduling on Hexagon.
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// Use a DFA based hazard recognizer.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonHazardRecognizer.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "post-RA-sched"
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void HexagonHazardRecognizer::Reset() {
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DEBUG(dbgs() << "Reset hazard recognizer\n");
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Resources->clearResources();
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PacketNum = 0;
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UsesDotCur = nullptr;
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DotCurPNum = -1;
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RegDefs.clear();
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}
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ScheduleHazardRecognizer::HazardType
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HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) {
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MachineInstr *MI = SU->getInstr();
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if (!MI || TII->isZeroCost(MI->getOpcode()))
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return NoHazard;
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if (!Resources->canReserveResources(*MI)) {
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DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
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HazardType RetVal = Hazard;
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if (TII->mayBeNewStore(*MI)) {
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// Make sure the register to be stored is defined by an instruction in the
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// packet.
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MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
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if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
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return Hazard;
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// The .new store version uses different resources so check if it
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// causes a hazard.
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MachineFunction *MF = MI->getParent()->getParent();
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MachineInstr *NewMI =
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MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
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MI->getDebugLoc());
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if (Resources->canReserveResources(*NewMI))
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RetVal = NoHazard;
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DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) << "\n");
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MF->DeleteMachineInstr(NewMI);
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}
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return RetVal;
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}
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if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
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DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " << *MI);
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return Hazard;
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}
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return NoHazard;
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}
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void HexagonHazardRecognizer::AdvanceCycle() {
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DEBUG(dbgs() << "Advance cycle, clear state\n");
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Resources->clearResources();
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if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) {
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UsesDotCur = nullptr;
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DotCurPNum = -1;
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}
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PacketNum++;
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RegDefs.clear();
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}
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/// If a packet contains a dot cur instruction, then we may prefer the
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/// instruction that can use the dot cur result. Or, if the use
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/// isn't scheduled in the same packet, then prefer other instructions
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/// in the subsequent packet.
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bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
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return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
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}
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void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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if (!MI)
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return;
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// Keep the set of definitions for each packet, which is used to determine
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// if a .new can be used.
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for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
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if (MO->isReg() && MO->isDef() && !MO->isImplicit())
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RegDefs.insert(MO->getReg());
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if (TII->isZeroCost(MI->getOpcode()))
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return;
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if (!Resources->canReserveResources(*MI)) {
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// It must be a .new store since other instructions must be able to be
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// reserved at this point.
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assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
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MachineFunction *MF = MI->getParent()->getParent();
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MachineInstr *NewMI =
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MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
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MI->getDebugLoc());
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assert(Resources->canReserveResources(*NewMI));
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Resources->reserveResources(*NewMI);
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MF->DeleteMachineInstr(NewMI);
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}
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else
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Resources->reserveResources(*MI);
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DEBUG(dbgs() << " Add instruction " << *MI);
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// When scheduling a dot cur instruction, check if there is an instruction
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// that can use the dot cur in the same packet. If so, we'll attempt to
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// schedule it before other instructions. We only do this if the use has
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// the same height as the dot cur. Otherwise, we may miss scheduling an
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// instruction with a greater height, which is more important.
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if (TII->mayBeCurLoad(*MI))
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for (auto &S : SU->Succs)
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if (S.isAssignedRegDep() && S.getLatency() == 0 &&
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SU->getHeight() == S.getSUnit()->getHeight()) {
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UsesDotCur = S.getSUnit();
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DotCurPNum = PacketNum;
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break;
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}
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if (SU == UsesDotCur) {
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UsesDotCur = nullptr;
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DotCurPNum = -1;
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}
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}
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