151 lines
3.3 KiB
LLVM
151 lines
3.3 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}break_inserted_outside_of_loop:
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; SI: [[LOOP_LABEL:[A-Z0-9]+]]:
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; Lowered break instructin:
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; SI: s_or_b64
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; Lowered Loop instruction:
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; SI: s_andn2_b64
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; s_cbranch_execnz [[LOOP_LABEL]]
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; SI: s_endpgm
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define void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) {
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main_body:
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%0 = and i32 %a, %tid
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%1 = trunc i32 %0 to i1
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br label %ENDIF
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ENDLOOP:
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store i32 0, i32 addrspace(1)* %out
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ret void
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ENDIF:
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br i1 %1, label %ENDLOOP, label %ENDIF
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}
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; FUNC-LABEL: {{^}}phi_cond_outside_loop:
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; FIXME: This could be folded into the s_or_b64 instruction
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; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0
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; SI: [[LOOP_LABEL:[A-Z0-9]+]]
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; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
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; SI_IF_BREAK instruction:
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; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
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; SI_LOOP instruction:
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; SI: s_andn2_b64 exec, exec, [[BREAK]]
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; SI: s_cbranch_execnz [[LOOP_LABEL]]
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; SI: s_endpgm
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define void @phi_cond_outside_loop(i32 %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%0 = icmp eq i32 %tid , 0
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br i1 %0, label %if, label %else
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if:
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br label %endif
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else:
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%1 = icmp eq i32 %b, 0
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br label %endif
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endif:
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%2 = phi i1 [0, %if], [%1, %else]
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br label %loop
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loop:
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br i1 %2, label %exit, label %loop
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exit:
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ret void
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}
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; FIXME: should emit s_endpgm
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; CHECK-LABEL: {{^}}switch_unreachable:
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; CHECK-NOT: s_endpgm
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; CHECK: .Lfunc_end2
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define void @switch_unreachable(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
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centry:
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switch i32 %x, label %sw.default [
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i32 0, label %sw.bb
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i32 60, label %sw.bb
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]
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sw.bb:
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unreachable
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sw.default:
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unreachable
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sw.epilog:
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ret void
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}
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declare float @llvm.fabs.f32(float) nounwind readnone
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; This broke the old AMDIL cfg structurizer
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; FUNC-LABEL: {{^}}loop_land_info_assert:
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; SI: s_cmp_gt_i32
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; SI-NEXT: s_cbranch_scc0 [[ENDPGM:BB[0-9]+_[0-9]+]]
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; SI: s_cmp_gt_i32
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; SI-NEXT: s_cbranch_scc1 [[ENDPGM]]
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; SI: [[INFLOOP:BB[0-9]+_[0-9]+]]
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; SI: s_branch [[INFLOOP]]
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; SI: [[ENDPGM]]:
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; SI: s_endpgm
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define void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {
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entry:
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%cmp = icmp sgt i32 %c0, 0
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br label %while.cond.outer
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while.cond.outer:
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%tmp = load float, float addrspace(1)* undef
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br label %while.cond
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while.cond:
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%cmp1 = icmp slt i32 %c1, 4
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br i1 %cmp1, label %convex.exit, label %for.cond
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convex.exit:
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%or = or i1 %cmp, %cmp1
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br i1 %or, label %return, label %if.end
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if.end:
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%tmp3 = call float @llvm.fabs.f32(float %tmp) nounwind readnone
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%cmp2 = fcmp olt float %tmp3, 0x3E80000000000000
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br i1 %cmp2, label %if.else, label %while.cond.outer
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if.else:
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store volatile i32 3, i32 addrspace(1)* undef, align 4
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br label %while.cond
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for.cond:
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%cmp3 = icmp slt i32 %c3, 1000
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br i1 %cmp3, label %for.body, label %return
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for.body:
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br i1 %cmp3, label %self.loop, label %if.end.2
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if.end.2:
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%or.cond2 = or i1 %cmp3, %arg
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br i1 %or.cond2, label %return, label %for.cond
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self.loop:
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br label %self.loop
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return:
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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attributes #0 = { nounwind readnone }
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