394 lines
11 KiB
LLVM
394 lines
11 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
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call void @llvm.AMDGPU.kill(float 0.0)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: ; BB#1:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
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call void @llvm.AMDGPU.kill(float -0.0)
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ret void
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}
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; FIXME: Ideally only one would be emitted
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg_x2:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: ; BB#1:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: ; BB#2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
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call void @llvm.AMDGPU.kill(float -0.0)
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call void @llvm.AMDGPU.kill(float -1.0)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: ; BB#1:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
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call void @llvm.AMDGPU.kill(float %x)
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ret void
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}
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; FIXME: Ideally only one would be emitted
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2_same:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: ; BB#1:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: ; BB#2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
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call void @llvm.AMDGPU.kill(float %x)
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call void @llvm.AMDGPU.kill(float %x)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: ; BB#1:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v1
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; CHECK-NEXT: ; BB#2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
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call void @llvm.AMDGPU.kill(float %x)
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call void @llvm.AMDGPU.kill(float %y)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: ; BB#1:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
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; CHECK-NEXT: ; BB#2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
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call void @llvm.AMDGPU.kill(float %x)
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%y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={VGPR7}"()
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call void @llvm.AMDGPU.kill(float %y)
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ret void
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}
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; FIXME: why does the skip depend on the asm length in the same block?
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; CHECK-LABEL: {{^}}test_kill_control_flow:
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; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0
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; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; BB#1:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
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; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; BB#3:
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; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_control_flow(i32 inreg %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={VGPR7}"()
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call void @llvm.AMDGPU.kill(float %var)
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br label %exit
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exit:
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_control_flow_remainder:
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; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0
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; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; BB#1: ; %bb
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: ;;#ASMEND
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; CHECK: v_mov_b32_e64 v8, -1
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; CHECK: ;;#ASMEND
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; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
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; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; BB#4:
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; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
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; CHECK: buffer_store_dword v8
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; CHECK: v_mov_b32_e64 v9, -2
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; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}:
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; CHECK: buffer_store_dword v9
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={VGPR7}"()
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%live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={VGPR8}"()
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call void @llvm.AMDGPU.kill(float %var)
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store volatile float %live.across, float addrspace(1)* undef
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%live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={VGPR9}"()
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br label %exit
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exit:
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%phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
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store float %phi, float addrspace(1)* undef
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_divergent_loop:
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; CHECK: v_cmp_eq_i32_e32 vcc, 0, v0
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; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; CHECK-NEXT: s_xor_b64 [[SAVEEXEC]], exec, [[SAVEEXEC]]
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; CHECK-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: s_cbranch_execz [[EXIT]]
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; CHECK: {{BB[0-9]+_[0-9]+}}: ; %bb.preheader
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; CHECK: s_mov_b32
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; CHECK: [[LOOP_BB:BB[0-9]+_[0-9]+]]:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
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; CHECK-NEXT: ; BB#3:
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; CHECK: buffer_load_dword [[LOAD:v[0-9]+]]
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; CHECK: v_cmp_eq_i32_e32 vcc, 0, [[LOAD]]
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; CHECK-NEXT: s_and_b64 vcc, exec, vcc
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; CHECK-NEXT: s_cbranch_vccnz [[LOOP_BB]]
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; CHECK-NEXT: {{^}}[[EXIT]]:
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; CHECK: s_or_b64 exec, exec, [[SAVEEXEC]]
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; CHECK: buffer_store_dword
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; CHECK: s_endpgm
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define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={VGPR7}"()
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call void @llvm.AMDGPU.kill(float %var)
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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%loop.cond = icmp eq i32 %vgpr, 0
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br i1 %loop.cond, label %bb, label %exit
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exit:
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store volatile i32 8, i32 addrspace(1)* undef
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ret void
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}
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; bug 28550
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; CHECK-LABEL: {{^}}phi_use_def_before_kill:
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; CHECK: v_cndmask_b32_e64 [[PHIREG:v[0-9]+]], 0, -1.0,
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; CHECK: v_cmpx_le_f32_e32 vcc, 0,
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; CHECK-NEXT: s_cbranch_execnz [[BB4:BB[0-9]+_[0-9]+]]
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; CHECK: exp
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; CHECK-NEXT: s_endpgm
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; CHECK: [[KILLBB:BB[0-9]+_[0-9]+]]:
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; CHECK: s_and_b64 vcc, exec,
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; CHECK-NEXT: s_cbranch_vccz [[PHIBB:BB[0-9]+_[0-9]+]]
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; CHECK: [[PHIBB]]:
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; CHECK: v_cmp_eq_f32_e32 vcc, 0, [[PHIREG]]
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; CHECK: s_and_b64 vcc, exec, vcc
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; CHECK: s_cbranch_vccz [[ENDBB:BB[0-9]+_[0-9]+]]
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; CHECK: ; BB#3: ; %bb10
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; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 9
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; CHECK: buffer_store_dword
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; CHECK: [[ENDBB]]:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @phi_use_def_before_kill() #0 {
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bb:
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%tmp = fadd float undef, 1.000000e+00
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%tmp1 = fcmp olt float 0.000000e+00, %tmp
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%tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
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call void @llvm.AMDGPU.kill(float %tmp2)
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br i1 undef, label %phibb, label %bb8
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phibb:
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%tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]
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%tmp6 = fcmp oeq float %tmp5, 0.000000e+00
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br i1 %tmp6, label %bb10, label %end
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bb8:
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store volatile i32 8, i32 addrspace(1)* undef
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br label %phibb
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bb10:
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store volatile i32 9, i32 addrspace(1)* undef
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br label %end
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end:
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ret void
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}
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; CHECK-LABEL: {{^}}no_skip_no_successors:
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; CHECK: v_cmp_nle_f32
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; CHECK: s_and_b64 vcc, exec,
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; CHECK: s_cbranch_vccz [[SKIPKILL:BB[0-9]+_[0-9]+]]
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; CHECK: ; BB#3: ; %bb6
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; CHECK: s_mov_b64 exec, 0
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; CHECK: [[SKIPKILL]]:
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; CHECK: v_cmp_nge_f32
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; CHECK: s_and_b64 vcc, exec, vcc
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; CHECK: s_cbranch_vccz [[UNREACHABLE:BB[0-9]+_[0-9]+]]
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; CHECK: [[UNREACHABLE]]:
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; CHECK-NEXT: .Lfunc_end{{[0-9]+}}
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define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
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bb:
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%tmp = fcmp ult float %arg1, 0.000000e+00
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%tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
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br i1 %tmp, label %bb6, label %bb3
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bb3: ; preds = %bb
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br i1 %tmp2, label %bb5, label %bb4
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bb4: ; preds = %bb3
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br i1 true, label %bb5, label %bb7
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bb5: ; preds = %bb4, %bb3
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unreachable
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bb6: ; preds = %bb
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call void @llvm.AMDGPU.kill(float -1.000000e+00)
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unreachable
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bb7: ; preds = %bb4
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ret void
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}
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; CHECK-LABEL: {{^}}if_after_kill_block:
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; CHECK: ; BB#0:
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; CHECK: s_and_saveexec_b64
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; CHECK: s_xor_b64
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; CHECK-NEXT: mask branch [[BB4:BB[0-9]+_[0-9]+]]
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; CHECK: v_cmpx_le_f32_e32 vcc, 0,
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; CHECK: [[BB4]]:
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; CHECK: s_or_b64 exec, exec
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; CHECK: image_sample_c
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; CHECK: v_cmp_neq_f32_e32 vcc, 0,
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; CHECK: s_and_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc
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; CHECK: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, exec
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; CHECK: mask branch [[END:BB[0-9]+_[0-9]+]]
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; CHECK-NOT: branch
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; CHECK: BB{{[0-9]+_[0-9]+}}: ; %bb8
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; CHECK: buffer_store_dword
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; CHECK: [[END]]:
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; CHECK: s_or_b64 exec, exec
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; CHECK: s_endpgm
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define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, <4 x i32> %arg2) #0 {
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bb:
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%tmp = fcmp ult float %arg1, 0.000000e+00
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br i1 %tmp, label %bb3, label %bb4
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bb3: ; preds = %bb
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call void @llvm.AMDGPU.kill(float %arg)
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br label %bb4
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bb4: ; preds = %bb3, %bb
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%tmp5 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %arg2, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp6 = extractelement <4 x float> %tmp5, i32 0
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%tmp7 = fcmp une float %tmp6, 0.000000e+00
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br i1 %tmp7, label %bb8, label %bb9
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bb8: ; preds = %bb9, %bb4
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store volatile i32 9, i32 addrspace(1)* undef
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ret void
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bb9: ; preds = %bb4
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ret void
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}
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declare void @llvm.AMDGPU.kill(float) #0
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declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) nounwind
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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