91 lines
3.6 KiB
LLVM
91 lines
3.6 KiB
LLVM
; Test the MSA integer to floating point conversion intrinsics that are encoded
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; with the 2RF instruction format.
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; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
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@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_ffint_s_w_test() nounwind {
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entry:
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%0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_s_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_ffint_s_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind
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; CHECK: llvm_mips_ffint_s_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ffint_s.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ffint_s_w_test
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;
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@llvm_mips_ffint_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_ffint_s_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_ffint_s_d_test() nounwind {
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entry:
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%0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_s_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_ffint_s_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind
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; CHECK: llvm_mips_ffint_s_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ffint_s.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ffint_s_d_test
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;
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@llvm_mips_ffint_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_ffint_u_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_ffint_u_w_test() nounwind {
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entry:
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%0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_u_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_ffint_u_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind
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; CHECK: llvm_mips_ffint_u_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ffint_u.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ffint_u_w_test
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;
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@llvm_mips_ffint_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_ffint_u_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_ffint_u_d_test() nounwind {
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entry:
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%0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_u_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_ffint_u_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.ffint.u.d(<2 x i64>) nounwind
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; CHECK: llvm_mips_ffint_u_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ffint_u.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ffint_u_d_test
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;
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