41 lines
1.5 KiB
LLVM
41 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s
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; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s
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; RUN: llc < %s -mtriple=i386 -mcpu=pentium-m | FileCheck %s
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; RUN: llc < %s -mtriple=i386 -mcpu=prescott | FileCheck %s
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; RUN: llc < %s -mtriple=i386 -mcpu=nocona | FileCheck %s
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;
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; Verify that scheduling puts some distance between a load feeding into
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; the address of another load, and that second load. This currently
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; happens during the post-RA-scheduler, which should be enabled by
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; default with the above specified cpus.
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@ptrs = external global [0 x i32*], align 4
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@idxa = common global i32 0, align 4
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@idxb = common global i32 0, align 4
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@res = common global i32 0, align 4
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define void @addindirect() {
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; CHECK-LABEL: addindirect:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl idxb, %ecx
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; CHECK-NEXT: movl idxa, %eax
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; CHECK-NEXT: movl ptrs(,%ecx,4), %ecx
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; CHECK-NEXT: movl ptrs(,%eax,4), %eax
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; CHECK-NEXT: movl (%ecx), %ecx
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; CHECK-NEXT: addl (%eax), %ecx
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; CHECK-NEXT: movl %ecx, res
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; CHECK-NEXT: retl
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entry:
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%0 = load i32, i32* @idxa, align 4
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%arrayidx = getelementptr inbounds [0 x i32*], [0 x i32*]* @ptrs, i32 0, i32 %0
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%1 = load i32*, i32** %arrayidx, align 4
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%2 = load i32, i32* %1, align 4
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%3 = load i32, i32* @idxb, align 4
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%arrayidx1 = getelementptr inbounds [0 x i32*], [0 x i32*]* @ptrs, i32 0, i32 %3
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%4 = load i32*, i32** %arrayidx1, align 4
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%5 = load i32, i32* %4, align 4
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%add = add i32 %5, %2
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store i32 %add, i32* @res, align 4
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ret void
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}
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