110 lines
3.2 KiB
LLVM
110 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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define <8 x i32> @a(<8 x i32> %a) nounwind {
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; SSE-LABEL: a:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: pslld $16, %xmm1
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; SSE-NEXT: psrad $16, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: a:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpslld $16, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $16, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpslld $16, %xmm0, %xmm0
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; AVX1-NEXT: vpsrad $16, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: a:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpslld $16, %ymm0, %ymm0
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; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = sext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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define <3 x i32> @b(<3 x i32> %a) nounwind {
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; SSE-LABEL: b:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: b:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $16, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $16, %xmm0, %xmm0
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; AVX-NEXT: retq
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%b = trunc <3 x i32> %a to <3 x i16>
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%c = sext <3 x i16> %b to <3 x i32>
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ret <3 x i32> %c
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}
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define <1 x i32> @c(<1 x i32> %a) nounwind {
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; ALL-LABEL: c:
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; ALL: # BB#0:
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; ALL-NEXT: movswl %di, %eax
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; ALL-NEXT: retq
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%b = trunc <1 x i32> %a to <1 x i16>
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%c = sext <1 x i16> %b to <1 x i32>
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ret <1 x i32> %c
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}
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define <8 x i32> @d(<8 x i32> %a) nounwind {
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; SSE-LABEL: d:
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; SSE: # BB#0:
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; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0]
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: d:
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; AVX1: # BB#0:
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: d:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1
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; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
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; AVX2-NEXT: retq
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = zext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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define <3 x i32> @e(<3 x i32> %a) nounwind {
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; SSE-LABEL: e:
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; SSE: # BB#0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: e:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6,7]
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; AVX-NEXT: retq
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%b = trunc <3 x i32> %a to <3 x i16>
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%c = zext <3 x i16> %b to <3 x i32>
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ret <3 x i32> %c
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}
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define <1 x i32> @f(<1 x i32> %a) nounwind {
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; ALL-LABEL: f:
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; ALL: # BB#0:
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; ALL-NEXT: movzwl %di, %eax
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; ALL-NEXT: retq
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%b = trunc <1 x i32> %a to <1 x i16>
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%c = zext <1 x i16> %b to <1 x i32>
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ret <1 x i32> %c
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}
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