104 lines
3.8 KiB
C++
104 lines
3.8 KiB
C++
//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file simulates the hardware responsible for retiring instructions.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "llvm-mca"
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namespace llvm {
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namespace mca {
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RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
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MaxRetirePerCycle(0) {
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assert(SM.isOutOfOrder() &&
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"RetireControlUnit is not available for in-order processors");
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// Check if the scheduling model provides extra information about the machine
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// processor. If so, then use that information to set the reorder buffer size
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// and the maximum number of instructions retired per cycle.
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if (SM.hasExtraProcessorInfo()) {
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const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
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if (EPI.ReorderBufferSize)
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AvailableEntries = EPI.ReorderBufferSize;
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MaxRetirePerCycle = EPI.MaxRetirePerCycle;
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}
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NumROBEntries = AvailableEntries;
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assert(NumROBEntries && "Invalid reorder buffer size!");
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Queue.resize(2 * NumROBEntries);
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}
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::dispatch(const InstRef &IR) {
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const Instruction &Inst = *IR.getInstruction();
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unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
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assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
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unsigned TokenID = NextAvailableSlotIdx;
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Queue[NextAvailableSlotIdx] = {IR, Entries, false};
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NextAvailableSlotIdx += std::max(1U, Entries);
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NextAvailableSlotIdx %= Queue.size();
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assert(TokenID < UnhandledTokenID && "Invalid token ID");
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AvailableEntries -= Entries;
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return TokenID;
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}
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const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const {
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const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
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#ifndef NDEBUG
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const Instruction *Inst = Current.IR.getInstruction();
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assert(Inst && "Invalid RUToken in the RCU queue.");
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#endif
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return Current;
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}
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unsigned RetireControlUnit::computeNextSlotIdx() const {
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const RetireControlUnit::RUToken &Current = getCurrentToken();
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unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);
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return NextSlotIdx % Queue.size();
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}
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const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const {
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return Queue[computeNextSlotIdx()];
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}
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void RetireControlUnit::consumeCurrentToken() {
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RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
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Current.IR.getInstruction()->retire();
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// Update the slot index to be the next item in the circular queue.
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CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);
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CurrentInstructionSlotIdx %= Queue.size();
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AvailableEntries += Current.NumSlots;
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Current = { InstRef(), 0U, false };
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}
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void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
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assert(Queue.size() > TokenID);
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assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
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assert(Queue[TokenID].Executed == false && "Instruction already executed!");
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Queue[TokenID].Executed = true;
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}
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#ifndef NDEBUG
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void RetireControlUnit::dump() const {
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dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
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<< ", Available ROB entries=" << AvailableEntries << " }\n";
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}
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#endif
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} // namespace mca
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} // namespace llvm
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