134 lines
4.7 KiB
LLVM
134 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
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define amdgpu_kernel void @sext_i16_to_i32_uniform(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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; GCN-LABEL: sext_i16_to_i32_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_sext_i32_i16 s0, s2
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; GCN-NEXT: s_add_i32 s0, s3, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%sext = sext i16 %a to i32
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%res = add i32 %b, %sext
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i64_uniform(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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; GCN-LABEL: sext_i16_to_i64_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xd
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
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; GCN-NEXT: s_add_u32 s4, s6, s4
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; GCN-NEXT: s_addc_u32 s5, s7, s5
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%sext = sext i16 %a to i64
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%res = add i64 %b, %sext
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store i64 %res, i64 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i32_divergent(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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; GCN-LABEL: sext_i16_to_i32_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%sext = sext i16 %divergent.a to i32
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store i32 %sext, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i64_divergent(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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; GCN-LABEL: sext_i16_to_i64_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%sext = sext i16 %divergent.a to i64
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store i64 %sext, i64 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i32_to_i64_uniform(i64 addrspace(1)* %out, i32 %a, i64 %b) {
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; GCN-LABEL: sext_i32_to_i64_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s6, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_ashr_i32 s7, s6, 31
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; GCN-NEXT: s_add_u32 s4, s4, s6
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; GCN-NEXT: s_addc_u32 s5, s5, s7
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%sext = sext i32 %a to i64
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%res = add i64 %b, %sext
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store i64 %res, i64 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i32_to_i64_divergent(i64 addrspace(1)* %out, i32 %a, i64 %b) {
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; GCN-LABEL: sext_i32_to_i64_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%divergent.a = add i32 %a, %tid
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%sext = sext i32 %divergent.a to i64
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store i64 %sext, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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