48 lines
2.9 KiB
YAML
48 lines
2.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+xnack -run-pass=si-form-memory-clauses -verify-machineinstrs -o - %s | FileCheck %s
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# Make sure that debug instructions do not change the bundling, and
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# the dbg_values which break the clause are inserted after the new
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# bundles.
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---
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name: sgpr_clause_dbg_value
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr4_sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24
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; CHECK-LABEL: name: sgpr_clause_dbg_value
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; CHECK: liveins: $sgpr4_sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0 :: (load (s32), addrspace 4)
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; CHECK-NEXT: DBG_VALUE [[S_LOAD_DWORD_IMM]], 0, 0
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 8, 0 :: (load (s32), addrspace 4)
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; CHECK-NEXT: DBG_VALUE [[S_LOAD_DWORD_IMM1]], 0, 0
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0 :: (load (s32), addrspace 4)
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 32, 0 :: (load (s32), addrspace 4)
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; CHECK-NEXT: DBG_VALUE [[S_LOAD_DWORD_IMM2]], 0, 0
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; CHECK-NEXT: DBG_VALUE [[S_LOAD_DWORD_IMM3]], 0, 0
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 64, 0 :: (load (s32), addrspace 4)
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; CHECK-NEXT: KILL [[COPY]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[S_LOAD_DWORD_IMM]], implicit [[S_LOAD_DWORD_IMM1]], implicit [[S_LOAD_DWORD_IMM2]], implicit [[S_LOAD_DWORD_IMM3]], implicit [[S_LOAD_DWORD_IMM4]]
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%0:sreg_64 = COPY $sgpr4_sgpr5
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 0, 0 :: (load (s32), align 4, addrspace 4)
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DBG_VALUE %1, 0, 0
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%2:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 8, 0 :: (load (s32), align 4, addrspace 4)
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DBG_VALUE %2, 0, 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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%3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0 :: (load (s32), align 4, addrspace 4)
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%4:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 32, 0 :: (load (s32), align 4, addrspace 4)
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DBG_VALUE %3, 0, 0
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DBG_VALUE %4, 0, 0
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%5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 64, 0 :: (load (s32), align 4, addrspace 4)
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S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5
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...
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