123 lines
2.9 KiB
LLVM
123 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Test for handling of AND with constant followed by a shift by constant. Often
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; we can replace these with a pair of shifts to avoid materializing a constant
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; for the and.
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define i32 @test1(i32 %x) {
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; RV32I-LABEL: test1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 5
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; RV32I-NEXT: andi a0, a0, -8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srliw a0, a0, 8
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: ret
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%a = lshr i32 %x, 5
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%b = and i32 %a, 134217720
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ret i32 %b
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}
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define i64 @test2(i64 %x) {
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; RV32I-LABEL: test2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a1, 27
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; RV32I-NEXT: srli a0, a0, 5
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a1, a1, 5
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; RV32I-NEXT: andi a0, a0, -8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 5
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; RV64I-NEXT: andi a0, a0, -8
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; RV64I-NEXT: ret
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%a = lshr i64 %x, 5
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%b = and i64 %a, 576460752303423480
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ret i64 %b
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}
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define i32 @test3(i32 %x) {
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; RV32I-LABEL: test3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: slli a0, a0, 14
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srliw a0, a0, 20
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; RV64I-NEXT: slli a0, a0, 14
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; RV64I-NEXT: ret
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%a = lshr i32 %x, 6
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%b = and i32 %a, 67092480
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ret i32 %b
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}
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define i64 @test4(i64 %x) {
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; RV32I-LABEL: test4:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a1, 26
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; RV32I-NEXT: srli a0, a0, 6
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a1, a1, 6
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; RV32I-NEXT: lui a2, 1048572
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test4:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 20
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; RV64I-NEXT: slli a0, a0, 14
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; RV64I-NEXT: ret
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%a = lshr i64 %x, 6
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%b = and i64 %a, 288230376151695360
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ret i64 %b
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}
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define i32 @test5(i32 %x) {
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; RV32I-LABEL: test5:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 10
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test5:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slliw a0, a0, 6
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; RV64I-NEXT: lui a1, 1048560
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = shl i32 %x, 6
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%b = and i32 %a, -65536
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ret i32 %b
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}
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define i64 @test6(i64 %x) {
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; RV32I-LABEL: test6:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a2, a0, 26
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; RV32I-NEXT: slli a1, a1, 6
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: srli a0, a0, 10
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test6:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 10
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; RV64I-NEXT: slli a0, a0, 16
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; RV64I-NEXT: ret
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%a = shl i64 %x, 6
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%b = and i64 %a, -65536
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ret i64 %b
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}
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