58 lines
2.1 KiB
LLVM
58 lines
2.1 KiB
LLVM
; RUN: opt -loop-vectorize -debug-only=loop-vectorize -disable-output -prefer-predicate-over-epilogue=scalar-epilogue 2>&1 < %s | FileCheck %s
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; REQUIRES: asserts
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target triple = "aarch64"
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; Test that shows how many registers the loop vectorizer thinks an illegal <VF x i1> will consume.
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; CHECK-LABEL: LV: Checking a loop in 'or_reduction_neon' from <stdin>
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; CHECK: LV(REG): VF = 32
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; CHECK-NEXT: LV(REG): Found max usage: 2 item
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; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 72 registers
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; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
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define i1 @or_reduction_neon(i32 %arg, ptr %ptr) {
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entry:
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br label %loop
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exit:
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ret i1 %reduction_next
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loop:
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%induction = phi i32 [ 0, %entry ], [ %induction_next, %loop ]
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%reduction = phi i1 [ 0, %entry ], [ %reduction_next, %loop ]
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%gep = getelementptr inbounds i32, ptr %ptr, i32 %induction
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%loaded = load i32, ptr %gep
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%i1 = icmp eq i32 %loaded, %induction
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%reduction_next = or i1 %i1, %reduction
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%induction_next = add nuw i32 %induction, 1
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%cond = icmp eq i32 %induction_next, %arg
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br i1 %cond, label %exit, label %loop, !llvm.loop !32
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}
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; CHECK-LABEL: LV: Checking a loop in 'or_reduction_sve'
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; CHECK: LV(REG): VF = 64
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; CHECK-NEXT: LV(REG): Found max usage: 2 item
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; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 136 registers
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; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
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define i1 @or_reduction_sve(i32 %arg, ptr %ptr) vscale_range(2,2) "target-features"="+sve" {
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entry:
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br label %loop
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exit:
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ret i1 %reduction_next
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loop:
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%induction = phi i32 [ 0, %entry ], [ %induction_next, %loop ]
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%reduction = phi i1 [ true, %entry ], [ %reduction_next, %loop ]
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%gep = getelementptr inbounds i32, ptr %ptr, i32 %induction
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%loaded = load i32, ptr %gep
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%i1 = icmp eq i32 %loaded, %induction
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%reduction_next = or i1 %i1, %reduction
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%induction_next = add nuw i32 %induction, 1
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%cond = icmp eq i32 %induction_next, %arg
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br i1 %cond, label %exit, label %loop, !llvm.loop !64
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}
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!32 = distinct !{!32, !33}
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!33 = !{!"llvm.loop.vectorize.width", i32 32}
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!64 = distinct !{!64, !65}
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!65 = !{!"llvm.loop.vectorize.width", i32 64}
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